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參數(shù)資料
| 型號(hào)： | ADS8402IPFBR |
| 英文描述： | 16-BIT, 1.25 MSPS, UNIPOLAR DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE |
| 中文描述： | 16位，1.25 MSPS的，單極差動(dòng)輸入，微功耗采樣模數(shù)位并行接口和參考轉(zhuǎn)爐 |
| 文件頁數(shù)： | 22/25頁 |
| 文件大小： | 212K |
| 代理商： | ADS8402IPFBR |
ADS8402
SLAS154B
–
DECEMBER 2002
–
REVISED MAY 2003
www.ti.com
22
+
_
+
THS4503
IN
–
ADS8402
IN+
_
+
VCC+
VCC
–
1 k
1 k
68 pF
68 pF
50
50
20 pF
RG
RS
RT
OCM
1 k
RG, RS, and RT should be chosen such that
RG + RS || RT = 1 k
VOCM = 2 V, +VCC = 7 V, and
–
VCC =
–
7 V
Figure 34. Using THS4503 With ADS8402
DIGITAL INTERFACE
Timing and Control
See the timing diagrams in the specifications section for detailed information on timing signals and their requirements.
The ADS8402 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8402 switches from the
sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal
is important to the performance of the converter. The BUSY output is brought high after CONVST goes low. BUSY
stays high throughout the conversion process and returns low when the conversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when
BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST
goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus
with the conversion.
Reading Data
The ADS8402 outputs full parallel data in two
’
s complement format as shown in Table 1. The parallel output is active
when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This
is 100 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attempted
within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword
read operations. BYTE is used whenever lower bits of the conversion result are output on the higher byte of the bus.
Refer to Table 1 for ideal output codes.
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| ADS8402IPFBRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 bit 1.25MSPS Parallel W/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8402IPFBT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 bit 1.25MSPS Parallel W/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8402IPFBTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B 1.25MSPS Para ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8405 | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE |
| ADS8405EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS8405 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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