參數(shù)資料
型號： ADS8382IBRHPT
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC28
封裝： 6 X 6 MM, GREEN, PLASTIC, QFN-28
文件頁數(shù)： 31/35頁
文件大小： 1416K
代理商： ADS8382IBRHPT
www.ti.com
TIMING REQUIREMENTS
(1) (2) (3) (4) (5) (6)
ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
ADS8382I/ADS8382IB
REF
PARAMETER
UNIT
FIGURE
MIN
TYP
MAX
Conversion time
43,44,
tconv
1000
1160
ns
45,46
tacq1
Acquisition time in normal mode
0.5
1000
s
43,44,46
tacq2
Acquisition time in nap mode (tacq2 = tacq1 + td18)
0.8
1000
s
45
CONVERSION AND SAMPLING
Quite sampling time (last toggle of interface signals to convert start
42,43,44,
tquiet1
command)(6)
30
ns
45,47,48,
49
Quite sampling time (convert start command to first toggle of interface
42,43,44,
tquiet2
signals)(6)
10
ns
45,47,48,
49
Quite conversion time (last toggle of interface signals to fall of BUSY)(6)
42,43,44,
tquiet3
600
ns
45,47,49
tsu1
Setup time, CONVST before BUSY fall
15
ns
43
tsu2
Setup time, CS before BUSY fall (only for conversion/sampling control)
20
ns
42,43
tsu4
Setup time, CONVST before CS rise (so CONVST can be recognized)
5
ns
43,44,46
th1
Hold time, CS after BUSY fall (only for conversion/sampling control)
0
ns
43
th3
Hold time, CONVST after CS rise
7
ns
45
th4
Hold time, CONVST after CS fall (to ensure width of CONVST_QUAL)(4)
20
ns
44
tw1
CONVST pulse duration
20
ns
45
tw2
CS pulse duration
10
ns
43,44
Pulse duration, time between conversion start command and conversion
tw5
1000
ns
46
abort command to successfully abort the ongoing conversion
DATA READ OPERATION
tcyc
SCLK period
25
ns
47,48,49
SCLK duty cycle
40%
60%
tsu5
Setup time, CS fall before first SCLK fall
10
ns
47
tsu6
Setup time, CS fall before FS rise
7
ns
48,49
tsu7
Setup time, FS fall before first SCLK fall
7
ns
48,49
th5
Hold time, CS fall after SCLK fall
3
ns
47
th6
Hold time, FS fall after SCLK fall
7
ns
48,49
tsu2
Setup time, CS fall before BUSY fall (only for read control)
20
ns
42,47
tsu3
Setup time, FS fall before BUSY fall (only for read control)
20
ns
42,49
th2
Hold time, CS fall after BUSY fall (only for read control)
15
ns
42,47
th8
Hold time, FS fall after BUSY fall (only for read control)
15
ns
42,49
tw2
CS pulse duration
10
ns
47
tw3
FS pulse duration
10
ns
48,49
MISCELLANEOUS
tw4
PD pulse duration for reset and power down
60
ns
55,56
All unspecified pulse durations
10
ns
(1)
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2)
All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.
(3)
All digital output signals loaded with 10-pF capacitors.
(4)
CONVST_QUAL is CONVST latched by a low value on CS (see Figure 41).
(5)
Reference figure indicated is only a representative of where the timing is applicable and is not exhaustive.
(6)
Quiet time zones are for meeting performance and not functionality.
5
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