參數(shù)資料
型號: ADS8365IPAG
英文描述: 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS
中文描述: 16位,AD7691的6通道同步采樣SAR類比數(shù)位轉(zhuǎn)換器
文件頁數(shù): 19/33頁
文件大小: 441K
代理商: ADS8365IPAG
www.ti.com
THEORY OF OPERATION
EXPLANATION OF CLOCK, RESET, FD, AND
EOC PINS
Clock
An external clock has to be provided for
the ADS8365. The maximum clock
frequency is 5MHz. The minimum clock
cycle is 200ns (see
Figure 1
, t
C1
), and
the clock has to remain high (
Figure 1
,
t
W1
) or low for at least 60ns.
RESET
Bringing the RESET signal low will
reset the ADS8365. Resetting clears
the control register and all the output
registers,
aborts
process,
and
t
C1
t
W1
t
W3
t
W2
t
D2
t
W4
t
D1
CLK
HOLD A
RESET
HOLD B
HOLD C
ADS8365
SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006
switches. The reset signal must stay
low for at least 20ns (see
Figure 27
,
t
W4
). The reset signal should be back
high for at least 20ns (
Figure 27
, t
)
before starting the next conversion
(negative hold edge).
The ADS8365 contains six 16-bit ADCs that can
operate simultaneously in pairs. The three hold
signals (HOLDA, HOLDB, and HOLDC) initiate the
conversion on the specific channels. A simultaneous
hold on all six channels can occur with all three hold
signals strobed together. The converted values are
saved in six registers. For each read operation, the
ADS8365 outputs 16 bits of information (16 data or 3
channel
address,
data
synchronization
information).
signals (A0, A1, and A2) select how the data are
read
from
the
ADS8365.
signals can define a selection of a single channel, a
cycle mode that cycles through all channels, or a
FIFO mode that sequences the data determined by
the order of the hold signals. The FIFO mode will
allow the six registers to be used by a single-channel
pair; therefore, three locations for CH X0 and three
locations for CH X1 can be updated before they are
read from the device.
EOC
End of conversion goes low when new
data from the internal ADC are latched
into the output registers, which usually
happens 16.5 clock cycles after hold
initiated the conversion. It remains low
for half a clock cycle. If more than one
channel
pair
simultaneously,
the
stored to the registers first (16.5 clock
cycles after hold), followed by the
B-channels one clock cycle later, and
finally the C-channels another clock
cycle later. If a reading (both RD and
CS are low) is in process, then the
latch process is delayed until the read
operation is finished.
valid,
The
and
address/mode
some
These
address/mode
is
A-channels
converted
get
FD
First data or A0 data are high if channel
A0 is chosen to be read next. In FIFO
mode, the channel (X0) that is written
to the FIFO first is latched into the A0
register. For example, when the FIFO
is empty, FD is 0. The first result
latched into the FIFO register A0 is,
therefore, chosen to be read next, and
FD rises. After the first channel is read
(one to three read cycles, depending
on BYTE and ADD), FD goes low
again.
any
conversion
the
in
closes
sampling
Figure 27. Start of the Conversion
19
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