參數(shù)資料
型號: ADS8361
英文描述: Dual, 500kSPS, 16-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 雙路,500kSPS,16位,2通道,同步采樣模擬數(shù)字轉換器
文件頁數(shù): 13/23頁
文件大小: 444K
代理商: ADS8361
ADS8361
SBOS230C
13
www.ti.com
tion). Twenty clock cycles are required to perform a single
conversion. Immediately following CONVST switching to
HIGH, the ADS8361 will switch from the sample mode to the
hold mode asynchronous to the external clock. The BUSY
output pin will then go HIGH and remain HIGH for the
duration of the conversion cycle. On the falling edge of the
first cycle of the external clock, the ADS8361 will latch in the
address for the next conversion cycle depending on the
status of the A0 pin (HIGH = Channel 1, LOW = Channel 0).
The address must be selected 15ns prior to the falling edge of
cycle one of the external clock and must remain
held
for 15ns
following the clock edge. For maximum throughput time, the
CONVST and RD pins should be tied together. CS must be
brought LOW to enable the CONVST and RD inputs. Data will
be valid on the falling edge of all 20 clock cycles per conver-
sion. The first bit of data will be a status flag for either Channel
0 or 1, the second bit will be a second status flag for either
Channel A or B. First and second bit will be 0 in Mode I. See
Table II below. The subsequent data will be MSB-first through
the LSB, followed by two zeros (see Table III and Figures 9
and 10).
CLOCK CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SERIAL DATA
CH0 OR CH1 CHA OR CHB
DB15 DB14 DB13 DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
TABLE III. Serial Data Output Format.
FIGURE 8. Ideal Conversion Characteristics (Condition: Single Ended, VCM = chXX
= 2.5V, V
REF
= 2.5V)
BIT 1
M1
BIT 2
CH0/1
MODE
M0
CHA/B
CHANNEL SELECTION
DATA OUTPUT
1
2
3
4
0
0
1
1
0
1
0
1
0
0
0
Ch0/1 Selected by A0
Ch0/1 Selected by A0
Ch0/1 Alternating
Ch0/1 Alternating
On Data A and B
Sequentially on Data A
On Data A and B
Sequentially on Data A
0 = A/1 = B
0
0 = A/1 = B
0/1
0/1
TABLE II. Mode Selection.
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
0000 0000 0000 0001
0000 0000 0000 0000
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
1111 1111 1111 1111
Binary Two
s Complement
BTC
D
VNFS = V
CM
V
REF
= 0V
0.000038V
0.000076V
0.000152V
2.499962V
2.500038V
VBPZ = 2.5V
Unipolar Analog Input Voltage
1LSB = 76
μ
V
V
CM
= 2.5V
V
REF
= 2.5V
4.999848V
VPFS
1LSB = 4.999924V
VPFS = V
CM
+ V
REF
= 5V
0
1
2
32767
32768
32769
65533
65534
65535
S
16-BIT
Bipolar Input, Binary Two
s Complement Output: (BTC)
Negative Full-Scale Code
Bipolar Zero Code
Positive Full-Scale Code
= VNFS = 8000
H
, Vcode = V
CM
V
REF
= VBPZ = 0000
H
, Vcode = V
CM
= VPFS = 7FFF
H
, Vcode = (V
CM
+ V
REF
)
1LSB
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