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參數(shù)資料
| 型號： | ADS8344 |
| 英文描述： | 16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位，8通道串行輸出采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 278K |
| 代理商： | ADS8344 |
12
ADS8344
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
BD
t
BDV
t
BTR
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
DCLK LOW
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
1.7
50
10
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
70
70
50
0
150
150
100
70
70
FIGURE 7. Ideal Input Voltages and Output Codes.
TABLE VII. Timing Specifications (+V
CC
= +4.75V to
+5.25V, T
A
= –40
°
C to +85
°
C, C
LOAD
= 50pF).
O
0V
FS = Full-Scale Voltage = V
REF
1 LSB = V
REF
/65,536
FS – 1 LSB
11...111
11...110
11...101
00...010
00...001
00...000
1 LSB
NOTE
(1)
: Voltage at converter input, after
multiplexer: +IN
–
(
–
IN). (See Figure 2.)
Input Voltage
(1)
(V)
Data Format
The ADS8344 output data is in straight binary format as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
POWER DISSIPATION
There are three power modes for the ADS8344: full power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The effects of these modes
varies depending on how the ADS8344 is being operated.
For example, at full conversion rate and 24-clocks per
conversion, there is very little difference between full power
mode and auto power-down, a shutdown (SHDN LOW) will
not lower power dissipation
When operating at full-speed and 24-clocks per conversion
(as shown in Figure 3), the ADS8344 spends most of its time
acquiring or converting. There is little time for auto power-
down, assuming that this mode is active. Thus, the differ-
ence between full power mode and auto power-down is
negligible. If the conversion rate is decreased by simply
slowing the frequency of the DCLK input, the two modes
remain approximately equal. However, if the DCLK fre-
quency is kept at the maximum rate during a conversion, but
conversions are simply done less often, then the difference
between the two modes is dramatic. In the latter case, the
converter spends an increasing percentage of its time in
power-down mode (assuming the auto power-down mode is
active).
If DCLK is active and CS is LOW while the ADS8344 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH.
Operating the ADS8344 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time “penalty” on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
NOISE
The noise floor of the ADS8344 itself is extremely low, as
can be seen from Figures 8 thru 11, and is much lower than
competing A/D converters. The ADS8344 was tested at both
5V and 2.7V and in both the internal and external clock
modes. A low level DC input was applied to the analog input
pins and the converter was put through 5,000 conversions.
The digital output of the A/D converter will vary in output
code due to the internal noise of the ADS8344. This is true
for all 16-bit SAR-type A/D converters. Using a histogram
to plot the output codes, the distribution should appear bell-
shaped with the peak of the bell curve representing the
nominal code for the input value. The
±
1
σ
,
±
2
σ
, and
±
3
σ
distributions will represent the 68.3%, 95.5%, and 99.7%,
respectively, of all codes. The transition noise can be calcu-
lated by dividing the number of codes measured by 6 and
this will yield the
±
3
σ
distribution or 99.7% of all codes.
Statistically, up to 3 codes could fall outside the distribution
when executing 1000 conversions. The ADS8344, with < 3
output codes for the
±
3
σ
distribution, will yield a <
±
0.5LSB
transition noise at 5V operation. Remember, to achieve this
low noise performance, the peak-to-peak noise of the input
signal and reference must be < 50
μ
V.
FIGURE 8. Histogram of 5000 Conversions of a DC Input at the
Code Transition, 5V operation external clock mode.
Code
4561
242
0
0
197
7FFE
7FFD
8001
8000
7FFF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8344E | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 8-Ch Serial Output Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8344E | 制造商:Texas Instruments 功能描述:IC's |
| ADS8344E | 制造商:Texas Instruments 功能描述:16BIT ADC SERIAL O/P SMD 8344 |
| ADS8344E/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 8-Ch Serial Output Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8344E/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 8-Ch Serial Output Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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