參數(shù)資料
型號(hào): ADS8344
英文描述: 16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 16位,8通道串行輸出采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 11/13頁(yè)
文件大?。?/td> 278K
代理商: ADS8344
11
ADS8344
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
BD
t
BDV
t
BTR
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
DCLK LOW
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
1.5
100
10
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
200
200
100
0
200
200
200
200
200
TABLE VI. Timing Specifications (+V
CC
= +2.7V to 3.6V,
T
A
= –40
°
C to +85
°
C, C
LOAD
= 50pF).
Since one clock cycle of the serial clock is consumed with
BUSY going high (while the MSB decision is being made),
16 additional clocks must be given to clock out all 16 bits of
data; thus, one conversion takes a minimum of 25 clock
cycles to fully read the data. Since most microprocessors
communicate in 8-bit transfers, this means that an additional
transfer must be made to capture the LSB.
There are two ways of handling this requirement. One is
shown in Figure 3, where the beginning of the next control
byte appears at the same time the LSB is being clocked out
of the ADS8344. This method allows for maximum through-
put and 24 clock cycles per conversion.
The other method is shown in Figure 5, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the DOUT line. BUSY and DOUT go into
a high-impedance state when CS goes high; after the next CS
falling edge, BUSY will go LOW.
Internal Clock Mode
In internal clock mode, the ADS8344 generates its own
conversion clock internally. This relieves the microproces-
sor from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate up to 2.4MHz. BUSY goes
HIGH at the start of conversion and then returns LOW when
the conversion is complete. During the conversion, BUSY
will remain LOW for a maximum of 8
μ
s. Also, during the
conversion, SCLK should remain LOW to achieve the best
noise performance. The conversion result is stored in an
internal register; the data may be clocked out of this register
any time after the conversion is complete.
t
ACQ
Acquire
Idle
Conversion
1
DCLK
CS
8
1
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2
S
DIN
A1
A0
SGL/
DIF
PD1 PD0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
8
1
8
Idle
1
8
Zero Filled...
If CS is LOW when BUSY goes LOW following a conver-
sion, the next falling edge of the external serial clock will
write out the MSB on the DOUT line. The remaining bits
(D14-D0) will be clocked out on each successive clock cycle
following the MSB. If CS is HIGH when BUSY goes LOW
then the DOUT line will remain in tri-state until CS goes
LOW (Figure 6). CS does not need to remain LOW once a
conversion has started. Note that BUSY is not tri-stated
when CS goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8344 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition
time t
ACQ
, is kept above 1.7
μ
s.
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for
the digital interface of the ADS8344.
t
ACQ
Acquire
Idle
Conversion
1
DCLK
CS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2
S
DIN
A1
A0
SGL/
DIF
PD1 PD0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Zero Filled...
FIGURE 5.
FIGURE 6.
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