參數(shù)資料
型號(hào): ADS831E
英文描述: MOSFET; Transistor Polarity:N Channel; Drain Source Voltage, Vds:25V; Continuous Drain Current, Id:0.75A; On-Resistance, Rds(on):0.35ohm; Rds(on) Test Voltage, Vgs:4.5V; Package/Case:3-SC-70; Leaded Process Compatible:No
中文描述: 8位,80MHz的采樣模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 2/11頁
文件大?。?/td> 179K
代理商: ADS831E
ADS831
2
SPECIFICATIONS
At T
A
= full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted.
ADS831E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
SPECIFIED TEMPERATURE RANGE
ANALOG INPUT
Standard Single-Ended Input Range
Optional Single-Ended Input Range
Common-Mode Voltage
Optional Differential Input Range
Analog Input Bias Current
Input Impedance
Track-Mode Input Bandwidth
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious Free Dynamic Range
(1)
f = 1MHz (–1dB input)
f = 10MHz (–1dB input)
Two-Tone Intermodulation Distortion
(3)
f = 9.5MHz and 9.9MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz
f = 10MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
f = 10MHz
Effective Number of Bits
(4)
, f = 1MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
Full-Scale Step Acquisition Time
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current
(5)
(V
= 5V)
Low Level Input Current (V
IN
= 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (I
OL
= 50
μ
A)
Low Output Voltage, (I
OL
= 1.6mA)
High Output Voltage, (I
OH
= 50
μ
A)
High Output Voltage, (I
OH
= 0.5mA)
Low Output Voltage, (I
OL
= 50
μ
A)
High Output Voltage, (I
OH
= 50
μ
A)
Output Capacitance
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (Referred to –FS)
Zero Error Drift (Referred to –FS)
Gain Error
(6)
Gain Error Drift
(6)
Power Supply Rejection of Gain
Internal REFT Tolerance
Internal REFB Tolerance
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
8 Guaranteed
–40 to +85
Bits
°
C
Ambient Air
2Vp-p
1Vp-p
1.5
2
3.5
3
V
V
V
V
μ
A
2.5
2Vp-p
2
3
1
1.25 || 5
300
M
|| pF
MHz
–3dBFS
10k
80M
Samples/s
Clk Cyc
4
±
0.25
±
0.35
±
1.0
LSB
LSB
Guaranteed
±
0.5
±
2.0
LSBs
67
65
dBFS
(2)
dBFS
50
–57
dBc
Referred to Full Scale
49
49
dB
dB
46
Referred to Full Scale
48.5
48.5
7.8
0.2
3
1.2
2
2.5
dB
dB
Bits
44
Input Tied to Common-Mode
LSBs rms
ns
ps rms
ns
ns
Start Conversion
100
10
μ
A
μ
A
V
V
pF
+3.5
+1.0
5
VDRV = 5V
+0.1
+0.2
V
V
V
V
V
V
pF
+4.9
+4.8
VDRV = 3V
+0.1
+2.8
5
at 25
°
C
–2.5
±
0.5
±
53
±
0.5
±
75
55
±
10
±
10
3.0
2.0
800
+2.5
%FS
ppm/
°
C
%FS
ppm/
°
C
dB
mV
mV
V
V
at 25
°
C
–2.5
+2.5
V
=
±
5%
Deviation from Ideal 3.0V
Deviation from Ideal 2.0V
±
100
±
100
V
– 1.25
REFT – 0.8
REFB + 0.8
1.25
REFT to REFB
CMOS Compatible
Rising Edge of Convert Clock
CMOS/TTL Compatible
Straight Offset Binary
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