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參數(shù)資料
| 型號： | ADS824E |
| 英文描述： | 10-Bit, 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，70MHz的采樣模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 185K |
| 代理商： | ADS824E |
12
ADS824
given by the following equation. If this value is near your
system requirements, input clock jitter must be reduced.
where:
IN
is input signal frequency
t
A
is rms clock jitter
Special consideration should be given to clock jitter, particu-
larly in undersampling applications. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of performance. When
digitizing at high sampling rates, the clock should have 50%
duty cycle (t
H
= t
L
), along with fast rise and fall times of 2ns
or less.
Digital Outputs
The output data format of the ADS824 is in positive Straight
Offset Binary code, see Tables I and II. This format can
easily be converted into the Binary Two’s Complement code
by inverting the MSB.
It is recommended to keep the capacitive loading on the data
lines as low as possible (
≤
15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS824 and affect the performance. If
necessary, external buffers or latches close to the converter’s
output pins may be used to minimize the capacitive loading.
They also provide the added benefit of isolating the ADS824
from any digital noise activities on the bus coupling back
high frequency noise.
+5V or +3V, the ADS824 produces corresponding logic
levels and can directly interface to the selected logic family.
The output stages are designed to supply sufficient current to
drive a variety of logic families. However, it is recom-
mended to use the ADS824 with +3V logic supply. This will
lower the power dissipation in the output stages due to the
lower output swing and reduce current glitches on the supply
line, which may affect the ac performance of the converter.
In some applications, it might be advantageous to decouple
the VDRV pin with additional capacitors or a pi-filter.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. The ADS824 should be treated
as an analog component. Whenever possible, the supply pins
should be powered by the analog supply. This will ensure
the most consistent results since digital supply lines often
carry high levels of noise which otherwise would be coupled
into the converter and degrade the achievable performance.
All ground connections on the ADS824 are internally joined
together, obviating the design of split ground planes. The
ground pins (1, 16, 26) should directly connect to an analog
ground plane, which covers the PC board area around the
converter. While designing the layout, it is important to keep
the analog signal traces separated from any digital lines to
prevent noise coupling onto the analog signal path. Because
of its high sampling rate the, ADS824 generates high fre-
quency current transients and noise (clock feedthrough) that
are fed back into the supply and reference lines. This
requires that all supply and reference pins be sufficiently
bypassed. Figure 9 shows the recommended decoupling
scheme for the ADS824. In most cases, 0.1
μ
F ceramic chip
capacitors at each pin are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin.
Therefore, they should be located as close to the supply pins
as possible. In addition, a larger bipolar capacitor (1
μ
F to
22
μ
F) should be placed on the PC board in proximity of the
converter circuit.
JitterSNR
t
rmssignaltormsnoise
IN
A
=
20
1
2
log
π
FIGURE 9. Recommended Bypassing for the Supply Pins.
+V
S
27
26
GND
ADS824
+
0.1μF
0.1μF
+V
S
15
16
GND
10μF
+5V
VDRV
28
0.1μF
+3/+5V
+FS –1LSB (IN = +3V, IN = +2V)
+1/2 Full Scale
Bipolar Zero (IN = IN = CMV)
–1/2 Full Scale
–FS (IN = +2V, IN = +3V)
11 1111 1111
11 0000 0000
10 0000 0000
01 0000 0000
00 0000 0000
STRAIGHT OFFSET BINARY
(SOB)
DIFFERENTIAL INPUT
TABLE II. Coding Table for Differential Input Configuration
and 2Vp-p Full-Scale Range.
+FS –1LSB (IN = REFT)
+1/2 Full Scale
Bipolar Zero (IN = CMV)
–1/2 Full Scale
–FS (IN = REFB)
11 1111 1111
11 0000 0000
10 0000 0000
01 0000 0000
00 0000 0000
SINGLE-ENDED INPUT
(IN = CMV)
STRAIGHT OFFSET BINARY
(SOB)
TABLE I. Coding Table for Single-Ended Input Configura-
tion with IN Tied to the Common-Mode Voltage
(CMV).
Digital Output Driver (VDRV)
The ADS824 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to
the other supply pins. By setting the voltage at VDRV to
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS824E/1K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
| ADS825 | 制造商:BB 制造商全稱:BB 功能描述:10-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTERS |
| ADS8254 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:16-BIT, 1-MSPS, PSEUDO-BIPOLAR DIFFERENTIAL SAR ADC WITH ON-CHIP ADC DRIVER (OPA) AND 4-CHANNEL DIFFERENTIAL MULTIPLEXER |
| ADS8254IBRGCR | 功能描述:模數(shù)轉換器 - ADC 16B,4Ch Diff Comp Acquisition Solution RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8254IBRGCT | 功能描述:模數(shù)轉換器 - ADC 16B,4Ch Diff Comp Acquisition Solution RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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