參數(shù)資料
型號(hào): ADS823E
英文描述: 10-Bit, 60MHz Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 10位,60MHz時(shí)采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 2/13頁(yè)
文件大?。?/td> 204K
代理商: ADS823E
2
ADS823, ADS826
SPECIFICATIONS
At T
A
= full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted.
CMOS
Straight Offset Binary
CMOS
Straight Offset Binary
ADS823E
ADS826E
(1)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RESOLUTION
10 Guaranteed
10 Guaranteed
Bits
°
C
SPECIFIED TEMPERATURE RANGE
Ambient Air
–40 to +85
–40 to +85
ANALOG INPUT
Standard Single-Ended Input Range
Optional Single-Ended Input Range
Common-Mode Voltage
Optional Differential Input Range
Analog Input Bias Current
Input Impedance
Track-Mode Input Bandwidth
2Vp-p
1Vp-p
1.5
2
3.5
3
6
6
6
6
V
V
V
V
μ
A
2.5
6
2Vp-p
2
3
6
6
1
6
6
6
1.25 || 5
300
M
|| pF
MHz
–3dBFS Input
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
10k
60M
6
6
Samples/s
Clk Cyc
5
6
DYNAMIC CHARACTERISTICS
Differential Linearity Error
(largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious Free Dynamic Range
(2)
f = 1MHz
f = 10MHz
Two-Tone Intermodulation Distortion
(4)
f = 9.5MHz and 9.9MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz
f = 10MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
f = 10MHz
Effective Number of Bits
(5)
, f = 1MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
(5)
Full-Scale Step Acquisition Time
±
0.25
±
0.25
±
1.0
6
6
6
LSB
LSB
Guaranteed
±
0.5
Guaranteed
6
±
2.0
6
LSBs
74
74
73
73
dBFS
(3)
dBFS
67
65
64
6
dBc
Referred to Full-Scale Sinewave
60
60
59
59
dB
dB
57
56
Referred to Full-Scale Sinewave
59
59
9.5
0.2
3
1.2
2
5
58
58
6
6
6
6
6
6
dB
dB
Bits
56
55
Input Grounded
LSBs rms
ns
ps rms
ns
ns
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current
(6)
(V
= 5V)
Low Level Input Current (V
IN
= 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
Start Conversion
+100
+10
6
6
μ
A
μ
A
V
V
pF
+3.5
+2.0
+1.0
+0.8
5
6
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (I
OL
= 50
μ
A to 1.6mA)
High Output Voltage, (I
OH
= 50
μ
A to 0.5mA)
Low Output Voltage, (I
OL
= 50
μ
A to 1.6mA)
High Output Voltage, (I
OH
= 50
μ
A to 0.5mA)
3-State Enable Time
3-State Disable Time
Output Capacitance
VDRV = 5V
+0.1
6
V
V
V
V
ns
ns
pF
+4.9
6
VDRV = 3V
+0.1
6
+2.8
6
OE = H to L
OE = L to H
2
2
5
40
10
6
6
6
6
6
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (referred to –FS)
Zero Error Drift (referred to –FS)
Midscale Offset Error
Gain Error
(7)
Gain Error Drift
(7)
Gain Error
(8)
Gain Error Drift
(8)
Power Supply Rejection of Gain
REFT Tolerance
REFB Tolerance
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
At 25
°
C
±
1.0
16
±
3.0
6
6
6
% FS
ppm/
°
C
% FS
% FS
ppm/
°
C
% FS
ppm/
°
C
dB
mV
mV
V
V
k
At 25
°
C
At 25
°
C
±
0.29
6
6
6
6
6
6
6
6
6
6
±
1.5
66
±
1.0
23
70
±
10
±
10
3.5
1.5
1.6
2.5
6
At 25
°
C
1.5
6
V
=
±
5%
50
6
Deviation From Ideal 3.5V
Deviation From Ideal 1.5V
±
25
±
25
6
6
6
6
REFB + 0.8
1.25
V
– 1.25
REFT – 0.8
6
6
REFT to REFB
CMOS-Compatible
Rising Edge of Convert Clock
TTL, +3V/+5V CMOS-Compatible
Rising Edge of Convert Clock
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