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ADS821
SBAS040B
2
RESOLUTION
Specified Temperature Range
10
+85
Bits
°
C
T
AMBIENT
–
40
ANALOG INPUT
Differential Full-Scale Input Range
Common-Mode Voltage
Analog Input Bandwidth (
–
3dB)
Small-Signal
Full-Power
Input Impedance
+1.25
+3.25
+2.25
V
V
–
20dBFS
(1)
Input
0dBFS Input
+25
°
C
+25
°
C
400
65
MHz
MHz
M
|| pF
1.25 || 4
DIGITAL INPUT
Logic Family
Convert Command
Start Conversion
ACCURACY
(2)
Gain Error
+25
°
C
Full
±
0.6
±
1.1
±
85
0.01
±
2.1
0.02
±
1.5
±
2.5
%
%
Gain Drift
Power-Supply Rejection of Gain
Input Offset Error
Power-Supply Rejection of Offset
ppm/
°
C
%FSR/%
%
%FSR/%
+V
S
=
±
5%
+25
°
C
Full
+25
°
C
0.15
±
3.5
0.15
+V
S
=
±
5%
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
10k
40M
Sample/s
Convert Cycle
6.5
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
t
H
= 13ns
(3)
+25
°
C
±
0.5
±
0.6
±
0.5
±
0.6
Tested
±
0.5
±
1.0
±
1.0
±
1.0
±
1.0
LSB
LSB
LSB
LSB
0
°
C to +70
°
C
+25
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
f = 12MHz
No Missing Codes
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (
–
1dBFS input)
±
2.0
LSB
+25
°
C
Full
+25
°
C
Full
60
54
58
54
70
67
63
62
dBFS
dBFS
dBFS
dBFS
f = 12MHz (
–
1dBFS input)
ADS821U
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
ELECTRICAL CHARACTERISTICS
At T
A
= +25
°
C, V
S
= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ABSOLUTE MAXIMUM RATINGS
(1)
+V
S
....................................................................................................... +6V
Analog Input ............................................................ 0V to (+V
S
+ 300mV)
Logic Input ............................................................... 0V to (+V
S
+ 300mV)
Case Temperature......................................................................... +100
°
C
Junction Temperature.................................................................... +150
°
C
Storage Temperature .................................................................... +125
°
C
External Top Reference Voltage (REFT)................................. +3.4V max
External Bottom Reference Voltage (REFB) ............................+1.1V min
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS821
SO-8
"
DW
"
–
40
°
C to +85
°
C
"
ADS821U
"
ADS821U
ADS821U/1K
Rails, 28
"
Tape and Reel, 1000
PACKAGE/ORDERING INFORMATION(1)
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
TTL/HCT Compatible CMOS
Falling Edge
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) Refer to Timing
Diagram footnotes for the differential linearity performance conditions for the SO and SSOP packages. (4) IMD is referred to the larger of the two input signals.
If referred to the peak envelope signal (
≈
0dB), the intermodulation products will be 7dB lower. (5) Based on (SINAD
–
1.76)/6.02. (6) No
“
rollover
”
of bits.