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參數(shù)資料
| 型號： | ADS821E |
| 英文描述： | 10-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，40MHz的采樣模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 384K |
| 代理商： | ADS821E |
www.ti.com
ADS821
SBAS040B
10
time-align it with the data created from the following quan-
tizer stages. This aligned data is fed into a digital error
correction circuit that can adjust the output data based on the
information found on the redundant bits. This technique gives
the ADS821 excellent differential linearity and ensures no
missing-codes at the 10-bit level.
The output data is available in Straight Offset Binary (SOB) or
Binary Two
’
s Complement (BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS821 can be configured in various
ways and driven with different circuits, depending on the
nature of the signal and the level of performance desired. The
ADS821 has an internal reference that sets the full-scale
input range of the A/D converter. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full-scale range of +1.25V
to +3.25V. Since each input is 2Vp-p and 180
°
out-of-phase
with the other, a 4V differential input signal to the quantizer
results. As shown in Figure 3, the positive full-scale reference
(REFT) and the negative full-scale reference (REFB) are
brought out for external bypassing. In addition, the common-
mode (CM) voltage may be used as a reference to provide the
appropriate offset for the driving circuitry. However, care must
be taken not to appreciably load this reference node. For
more information regarding external references, single-ended
inputs, and ADS821 drive circuits, refer to the applications
section.
For most applications, the clock duty should be set to
50%. For applications requiring no missing codes, how-
ever, a slight skew in the duty cycle will improve DNL
performance for conversion rates > 35MHz and input
frequencies < 2MHz (see Timing Diagram) in the SO
package. For the best performance in the SSOP pack-
age, the clock should be skewed under all input frequen-
cies with conversion rates > 35MHz. A possible method
for skewing the 50% duty cycle source is shown in Figure 4.
FIGURE 3. Internal Reference Structure.
CLOCK REQUIREMENTS
The CLK pin accepts a CMOS level clock input. Both the
rising and falling edges of the externally applied clock con-
trols the various interstage conversions in the pipeline. There-
fore, the clock signal
’
s jitter, rise-and-fall times and duty cycle
can affect conversion performance.
Low clock
jitter
is critical to SNR performance in fre-
quency-domain signal environments.
Clock
rise and fall times
should be as short as possible
(< 2ns for best performance).
FIGURE 4. Clock Skew Circuit.
DIGITAL OUTPUT DATA
The 10-bit output data is provided at CMOS logic levels. There
is a 6.5 clock cycle data latency from the start convert signal
to the valid output data. The standard output coding is Straight
Offset Binary where a full-scale input signal corresponds to all
“
1
’
s
”
at the output. This condition is met with pin 19 LOW or
Floating due to an internal pull-down resistor. By applying a
high voltage to this pin, a BTC output will be provided where
the most significant bit is inverted. The digital outputs of the
ADS821 can be set to a high impedance state by driving
OE
(pin 18) with a logic HIGH. Normal operation is achieved with
pin 18 LOW or Floating due to internal pull-down resistors. This
function is provided for testability purposes and is not meant to
drive digital buses directly or be dynamically changed during
the conversion process.
OUTPUT CODE
SOB
PIN 19
BTC
PIN 19
HIGH
DIFFERENTIAL INPUT
(1)
FLOATING or LOW
+FS (IN = +3.25V, IN = +1.25V)
+FS
–
1LSB
+FS
–
2LSB
+3/4 Full-Scale
+1/2 Full-Scale
+1/4 Full-Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–
1LSB
–
1/4 Full-Scale
–
1/2 Full-Scale
–
3/4 Full-Scale
–
FS + 1LSB
–
FS (IN = +1.25V, IN = +3.25V)
1111111111
1111111111
1111111110
1110000000
1100000000
1010000000
1000000001
1000000000
0111111111
0110000000
0100000000
0010000000
0000000001
0000000000
0111111111
0111111111
0111111110
0110000000
0100000000
0010000000
0000000001
0000000000
1111111111
1110000000
1100000000
1010000000
1000000001
1000000000
NOTE: (1) In the single-ended input mode, +FS = +4.25V and
–
FS = +0.25V.
TABLE I. Coding Table for the ADS821.
+1.25V
+3.25V
2k
2k
0.1
μ
F
0.1
μ
F
+2.25V
REFT
REFB
CM
ADS821
To
Internal
Comparators
21
22
23
0.1
μ
F
R
V
2k
V
DD
0.1
μ
F
V
DD
CLK
OUT
CLK
IN
IC2
IC1
IC1, IC2 = ACT04
R
V
= 217
, Typical
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS821E/1K | 制造商:BB 制造商全稱:BB 功能描述:10-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS821U | 功能描述:模數(shù)轉換器 - ADC 10-Bit 40 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS821U | 制造商:Texas Instruments 功能描述:10 bit sampling analog/digital converter |
| ADS821U | 制造商:Texas Instruments 功能描述:IC 10BIT ADC 40SPS 28-SOIC |
| ADS821U-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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