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參數(shù)資料
| 型號(hào)： | ADS808 |
| 英文描述： | 12-Bit, 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 12位，70MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大小： | 364K |
| 代理商： | ADS808 |
ADS808
SBAS179C
13
www.ti.com
CLK
CLK
ADS808
0.1
μ
F
1:1
Square Wave
Clock Source
FIGURE 11. Connecting a Ground Referenced Square Wave
Clock Source to the ADS808 Using a RF Trans-
former.
DIGITAL INPUTS AND OUTPUTS
CLOCK INPUT
Unlike most A/D converters, the ADS808 contains an internal
clock conditioning circuitry. This enables the converter to
adapt to a variety of application requirements and different
clock sources. Some interface examples are given in the
following section. With no input signal connected to either
clock pin, the threshold level is set to about +1.6V by the
on-chip resistive voltage divider, as shown in Figure 9. The
parallel combination of R
1
|| R
2
and R
3
|| R
4
sets the input
impedance of the clock inputs (CLK,
CLK
) to approximately
2.7k
single-ended, or 5.4k
differentially. The associated
ground-referenced input capacitance is approximately 5pF
for each input. If a logic voltage other than the nominal +1.6V
is desired, the clock inputs can be externally driven to
establish an alternate threshold voltage.
R
1
8.5k
ADS808
R
3
8.5k
+5V
R
2
4k
CLK
CLK
R
4
4k
Applying a single-ended clock signal will provide satisfactory
results in many applications. However, unbalanced high-
speed logic signals often introduce a high amount of distur-
bances, such as ringing or ground bouncing. Also, a high
amplitude may cause the clock signal to have unsymmetrical
rise and fall times, potentially effecting the converter
’
s distor-
tion performance. Proper termination practice and a clean
PCB layout will help to keep those effects to a minimum.
To take full advantage of the excellent distortion performance
of the ADS808, it is recommended to drive the clock inputs
differentially. A low-level, differential clock improves the digi-
tal feedthrough immunity and minimizes the effect of modu-
lation between the signal and the clock. Figure 11 illustrates
a simple method of converting a square wave clock from
single-ended to differential using a RF transformer. Small
surface-mount transformers are readily available from sev-
eral manufacturers (e.g.: model ADT1-1 by Mini-Circuits). A
capacitor in series with the primary side may be inserted to
block any DC voltage present in the signal. Since the clock
inputs are self-biased, the secondary side connects directly
to the two clock inputs of the converter.
CLK
CLK
ADS808
47nF
TTL/CMOS
Clock Source
(3V/5V)
FIGURE 9. The Differential Clock Inputs are Internally Biased.
FIGURE 10. Single-Ended TTL/CMOS Clock Source.
The ADS808 can be interfaced to standard TTL or CMOS
logic and accepts 3V or 5V compliant logic levels. In this case,
the clock signal should be applied to the CLK input, while the
complementary clock input (
CLK
) should be bypassed to
ground by a low-inductance ceramic chip capacitor, as shown
in Figure 10. Depending on the quality of the signal, inserting
a series damping resistor may be beneficial to reduce ringing.
When digitizing at high sampling rates (f
S
> 50MHz), the clock
should have a 50% duty cycle (t
H
= t
L
) to maintain a good
distortion performance.
The clock inputs of the ADS808 can be connected in a
number of ways. However, the best performance is obtained
when the clock input pins are driven differentially. When
operating in this mode, the clock inputs accommodate signal
swings ranging from 2.5Vp-p down to 0.5Vp-p, differentially.
This allows direct interfacing of clock sources, such as
voltage-controlled crystal oscillators (VCXO) to the ADS808.
The advantage here is the elimination of external logic
usually necessary to convert the clock signal into a suitable
logic (TTL or CMOS) signal, that otherwise would create an
additional source of jitter. In any case, a very low-jitter clock
is fundamental to preserving the excellent AC performance
of the ADS808. The converter itself is specified for a very low
0.25ps (rms) jitter, characterizing the outstanding capability
of the internal clock and track-and-hold circuitry. Generally,
as the input frequency increases, the clock jitter becomes
more dominant in maintaining a good SNR. This is particu-
larly critical in IF sampling applications where the sampling
frequency is lower than the input frequency (or
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS808Y/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 70MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS808Y/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 70MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS808Y/2K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 70MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS808Y/2KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 70MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS809 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
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