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參數(shù)資料
| 型號(hào)： | ADS805 |
| 英文描述： | 12-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 12位，20MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 260K |
| 代理商： | ADS805 |
12
ADS805
necessary, external buffers or latches may be used which
provide the added benefit of isolating the ADS805 from any
digital noise activities on the bus coupling back high fre-
quency noise. In addition, resistors in series with each data
line may help maintain the ac performance of the ADS805.
Their use depends on the capacitive loading seen by the
converter. Values in the range of 100
to 200
will limit
the instantaneous current the output stage has to provide for
recharging the parasitic capacitances, as the output levels
change from L to H or H to L.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multi-layer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. It is recommended that the
analog and digital ground pins of the ADS805 be joined
together at the IC and be connected only to the analog
ground of the system.
The ADS805 has analog and digital supply pins, however
the converter should be treated as an analog component and
all supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise that would otherwise be
coupled into the converter and degrade the achievable per-
formance.
Because of the pipeline architecture, the converter also
generates high frequency current transients and noise that
are fed back into the supply and reference lines. This
requires that the supply and reference pins be sufficiently
bypassed. Figure 12 shows the recommended decoupling
scheme for the analog supplies. In most cases, 0.1
μ
F ce-
ramic chip capacitors are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin.
Therefore, they should be located as close to the supply pins
as possible. In addition, a larger size bipolar capacitor (1
μ
F
to 22
μ
F) should be placed on the PC board in close proxim-
ity to the converter circuit.
FIGURE 11. External Logic for Decoding Underrange and
Overrange Condition.
OVR
MSB
Under = H
Over = H
CLOCK INPUT REQUIREMENTS
Clock jitter is critical to the SNR performance of high speed,
high resolution analog-to-digital converters. It leads to aper-
ture jitter (t
A
) which adds noise to the signal being con-
verted. The ADS805 samples the input signal on the rising
edge of the CLK input. Therefore, this edge should have the
lowest possible jitter. The jitter noise contribution to total
SNR is given by the following equation. If this value is near
your system requirements, input clock jitter must be re-
duced.
Where:
IN
is Input Signal Frequency
t
A
is rms Clock Jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should
have a 50% duty cycle (t
H
= t
L
), along with fast rise and fall
times of 2ns or less.
DIGITAL OUTPUTS
The digital outputs of the ADS805 are designed to be
compatible with both high speed TTL and CMOS logic
families. The driver stage for the digital outputs is supplied
through a separate supply pin, VDRV, which is not con-
nected to the analog supply pins. By adjusting the voltage on
VDRV, the digital output levels will vary respectively.
Therefore, it is possible to operate the ADS805 on a +5V
analog supply while interfacing the digital outputs to
3V-logic with the VDRV pin tied to the +3V digital supply.
It is recommended to keep the capacitive loading on the data
lines as low as possible (
≤
15pF). Larger capacitive loads
demand higher charging currents as the output are changing.
Those high current surges can feed back to the analog
portion of the ADS805 and influence the performance. If
FIGURE 12. Recommended Bypassing for Analog Supply
Pins.
+V
S
27
26
GND
ADS805
+
0.1μF
0.1μF
+V
S
16
17
GND
2.2μF
VDRV
28
0.1μF
+5V/+3V
+5V
JitterSNR
rmssignaltormsnoise
IN A
=
20
1
2
log
π
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PDF描述 |
|---|---|
| ADS805E | 12-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS805U | 12-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS807 | 12-Bit, 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS807E | 12-Bit, 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS805E | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 20 MSPS Int/Ext Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS805E/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 20 MSPS Int/Ext Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS805E/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 20 MSPS Int/Ext Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS805EG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 20 MSPS Int/Ext Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS805U | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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