參數(shù)資料
型號(hào): ADS800U
英文描述: 12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 12位,40MHz的采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 9/17頁(yè)
文件大?。?/td> 368K
代理商: ADS800U
ADS800
SBAS035B
9
www.ti.com
THEORY OF OPERATION
The ADS800 is a high-speed, sampling A/D converter with
pipelining. It uses a fully differential architecture and digital
error correction to ensure 12-bit resolution. The differential
track-and-hold circuit is shown in Figure 1. The switches are
controlled by an internal clock which has a non-overlapping
2-phase signal,
φ
1 and
φ
2. At the sampling time, the input
signal is sampled on the bottom plates of the input capaci-
tors. In the next clock phase,
φ
2, the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time,
the charge redistributes between C
I
and C
H
, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. The
track-and-hold circuit can also convert a single-ended input
signal into a fully differential signal for the quantizer.
The pipelined quantizer architecture has 11 stages with each
stage containing a 2-bit quantizer and a 2-bit Digital-to-
Analog Converter (DAC), as shown in Figure 2. Each 2-bit
quantizer stage converts on the edge of the sub-clock, which
is twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to time-
FIGURE 2. Pipeline A/D Converter Architecture.
FIGURE 1. Input Track-and-Hold Configuration with Timing
Signals.
φ
1
φ
1
φ
2
φ
1
φ
1
φ
1
φ
1
φ
1
φ
2
φ
1
φ
2
φ
1
φ
2
IN
IN
OUT
OUT
Op Amp
Bias
V
CM
Op Amp
Bias
V
CM
C
H
C
I
C
I
C
H
Input Clock (50%)
Internal Non-Overlapping Clock
B1 (MSB)
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12 (LSB)
2-Bit
Flash
Input
T/H
Digital Delay
x2
x2
2-Bit
DAC
2-Bit
DAC
2-Bit
DAC
2-Bit
Flash
Digital Delay
2-Bit
Flash
Digital Delay
2-Bit
Flash
Digital Delay
x2
D
IN
IN
STAGE 1
STAGE 2
STAGE 10
STAGE 11
Σ
+
Σ
+
Σ
+
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