參數(shù)資料
型號: ADS7864Y/250G4
廠商: Texas Instruments
文件頁數(shù): 7/27頁
文件大?。?/td> 0K
描述: IC 12BIT 500KHZ 6CH ADC 48-TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 250
位數(shù): 12
采樣率(每秒): 500k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 50mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 12 個單端,雙極;6 個差分,雙極
配用: 296-30697-ND - EVAL MODULE FOR ADS7864M
www.ti.com
ADS7864
SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005
other channels are already in the hold mode but not
Once a particular hold signal goes low, further im-
converted, then the conversion of channel X is put in
pulses of this hold signal are ignored until the
the queue until the previous conversion has been
conversion is finished or the part is reset. When the
completed. If more than one channel goes into hold
conversion is finished (BUSY signal goes high), the
mode within one clock cycle, then channel A will be
sampling switches will close and sample the selected
converted first if HOLDA is one of the triggered hold
channel. The start of the next conversion must be
signals. Next, channel B will be converted, and last,
delayed to allow the input capacitor of the ADS7864
channel C. If it is important to detect a hold command
to be fully charged. This delay time depends on the
during a certain clock cycle, then the falling edge of
driving amplifier, but should be at least 175ns
the hold signal has to occur at least 10ns before the
(see Figure 27, t4).
falling edge of the clock. (see Figure 26, t1). The hold
The ADS7864 can also convert one channel continu-
signal can remain low without initiating a new conver-
ously, as it is shown in Figure 27 with channel B.
sion. The hold signal has to be high for at least 15ns
Therefore, HOLDA and HOLDC are kept high all the
(see Figure 26, t2) before it is brought low again and
time. To gain acquisition time, the falling edge of
hold has to stay low for at least 20ns (see Figure 26,
HOLDB takes place just before the falling edge of
t3).
clock. One conversion requires 16 clock cycles. Here,
In the example of Figure 26, the signal HOLDB goes
data is read after the next conversion is initiated by
low first and channel B0 and B1 will be converted
HOLDB. To read data from channel B, A1 is set high
first. The falling edges of HOLDA and HOLDC occur
and A2 is low. As A0 is low during the first reading
within the same clock cycle. Therefore, the channels
(A2 A1 A0 = 010) data B0 is put to the output. Before
A0 and A1 will be converted as soon as the channels
the second RD, A0 switches high (A2 A1 A0 = 011)
B0 and B1 are finished (plus acquisition time). When
so data from channel B1 is read.
the A-channels are finished, the C-channels will be
converted. The second HOLDA signal is ignored, as
the A-channels are not converted at this point in time.
Table 1. Timing Specifications
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
HOLD (A, B, C) before falling edge of clock
10
ns
t2
HOLD high time to be recognized again
15
ns
t3
HOLD low time
20
ns
t4
Input capacitor charge time
175
ns
t5
Clock period
125
ns
t6
Clock high time
40
ns
t7
Clock low time
40
ns
t8
Reset pulse width
20
ns
t9
First hold after reset
20
ns
t10
Conversion time
12.5 × t5
ns
t11
Successive conversion time (16 × t5)
2
s
t12
Address setup before RD
10
ns
t13
CS before end of RD
30
ns
t14
RD high time
30
ns
15
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