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| 型號(hào)： | ADS7863IRGET |
| 英文描述： | Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 雙路，1.5Msps的，12位，2通道，同步采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 8/30頁(yè) |
| 文件大?。?/td> | 637K |
| 代理商： | ADS7863IRGET |
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P
CLOCK
CONVST
12ns
Cyc e 1
Cyc e 2
A
B
C
12ns
TBD
TBD
TIMING REQUIREMENTS
(1)
Over recommended operating free-air temperature range at –40
°
C to +125
°
C, AV
DD
= 5V, and BV
DD
= 2.7V to 5V, unless
otherwise noted.
ADS7863
SBAS383–JUNE 2007
TIMING CHARACTERISTICS (continued)
NOTE: All CONVST commands that occur more than 12ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands that occur
TBD
ns after the
rising edge of cycle ‘1’ or 12ns before the rising edge of cycle 2 (Region ‘B’) initiate a conversion on the rising edge
of cycle ‘2’. All CONVST commands that occur
TBD
ns after the rising edge of cycle ‘2’ (Region ‘C’) initiate a
conversion on the rising edge of the next clock period.
The CONVST pin should never be switched from LOW to HIGH in the region 12ns prior to the rising edge of the
CLOCK and
TBD
ns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could
begin on either the same rising edge of the CLOCK or the following edge.
Figure 2. CONVST Timing
ADS7863
MIN
541.67
125
1
41.67
5
5
15
10
5
10
5
15
15
20
SYMBOL
t
CONV
t
ACQ
f
CLOCK
T
CLOCK
t
CKL
t
CKH
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
PARAMETER
COMMENTS
MAX
UNIT
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conversion time
Acquisition time
CLOCK frequency
CLOCK period
CLOCK low time
CLOCK high time
CONVST high time
SDI setup time to CLOCK falling edge
SDI hold time to CLOCK falling edge
RD high setup time to CLOCK falling edge
RD high hold time to CLOCK falling edge
CONVST low time
RD low time relative to CLOCK falling edge
CS low to SDOx valid
SDOx data setup time to CLOCK falling
edge
SDOx data hold time to CLOCK falling edge
CONVST setup time to rising edge of
CLOCK
CLOCK rising edge to BUSY low delay
CS low to RD high delay
f
CLOCK
= 24MHz
f
CLOCK
= 24MHz
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
See
Figure 1
24
1000
t
9
See
Figure 1
25
ns
t
10
See
Figure 1
5
ns
t
11
See
Figure 1
12
ns
t
12
t
13
See
Figure 1
See
Figure 1
3
ns
ns
10
(1)
All input signals are specified with t
R
= t
F
= 1.5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
8
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