參數(shù)資料
型號(hào)： ADS7863IRGET
英文描述： Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述： 雙路，1.5Msps的，12位，2通道，同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 15/30頁(yè)
文件大?。?/td> 637K
代理商： ADS7863IRGET
www.ti.com
P
MODE II
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
C[1:0] = '00'
P[1:0] = '00'
CHx0 Next
No Features
C[1:0] = '11'
P[1:0] = '11'
CHx1 Next
No Features
C[1:0] = '00'
P[1:0] = '00'
CHx0 Next
No Features
C[1:0] = '11'
P[1:0] = '11'
CHx1 Next
No Features
SDI Ignored
SDI Ignored
A
A
A
CHx
B
B
CHx
12-Bit
Data CHB1
12-Bit
Data CHA0
12-Bit
Data CHA0
12-Bit
Data CHB0
12-Bit
Data CHA1
Previous 12-Bit
Data CHAx
Data CHBx
High-Z
No Conversion,
Read Access Only
No Conversion,
Read Access Only
Conversion
of Both CHx0
Conversion
of Both CHx1
Conversion
of Both CHx0
Previous Conversion
of Both CHxx
0 s
m
0.5 s
m
1.0 s
m
1.5 s
m
2.0 s
m
2.5 s
m
3.0 s
m
1
161
161
161
161
161
1
CLOCK
CONVST
SDI
M0
M1
RD
CS
SDOA
SDOB
BUSY
Previous 12-Bit
ADS7863
SBAS383–JUNE 2007
(instead of 16 cycles, if M1 = 0), the ADS7863
requires 1
μ
s to perform a complete conversion/read
cycle. If the CONVST signal is issued every 0.5
μ
s
(which is required for the RD signal) as in Mode I,
every second pulse is ignored; see
Figure 17
.
With M0 = 0 and M1 set to '1', the ADS7863 also
operates in manual channel control mode and
outputs data on the SDOA pin only while SDOB is
set to tri-state. All other pins function in the same
manner as they do in Mode I. Because it takes 32
clock cycles to output the results from both ADCs
The output data consist of a '0' followed by an ADC
indicator ('0' for CHAx or '1' for CHBx), 12 bits of
conversion results, and another '00'.
Figure 17. Mode II Timing Diagram (M0 = 0; M1 = 1)
15
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ADS7864 制造商:BB 制造商全稱:BB 功能描述:500kHz, 12-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
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