參數(shù)資料
型號: ADS7843E
元件分類: 通用總線功能
英文描述: CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter 16-PDIP -55 to 125
中文描述: 觸摸屏控制器
文件頁數(shù): 10/12頁
文件大?。?/td> 163K
代理商: ADS7843E
10
ADS7843
16-Clocks per Conversion
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 6. This figure also shows pos-
sible serial communication occurring with other serial pe-
ripherals between each byte transfer between the processor
and the converter. This is possible provided that each
conversion completes within 1.6ms of starting. Otherwise,
the signal that has been captured on the input sample/hold
may droop enough to affect the conversion result. Note that
the ADS7843 is fully powered while other serial communi-
cations are taking place during a conversion.
Digital Timing
Figure 7 and Table VI provide detailed timing for the digital
interface of the ADS7843.
15-Clocks per Conversion
Figure 8 provides the fastest way to clock the ADS7843.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively in-
creases the maximum conversion rate of the converter be-
yond the values given in the specification tables, which
assume 16 clock cycles per conversion.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
Acquisition Time
1.5
μ
s
t
DS
DIN Valid Prior to DCLK Rising
100
ns
t
DH
DIN Hold After DCLK HIGH
10
ns
t
DO
DCLK Falling to DOUT Valid
200
ns
t
DV
CS Falling to DOUT Enabled
200
ns
t
TR
CS Rising to DOUT Disabled
200
ns
t
CSS
CS Falling to First DCLK Rising
100
ns
t
CSH
CS Rising to DCLK Ignored
0
ns
t
CH
DCLK HIGH
200
ns
t
CL
DCLK LOW
200
ns
t
BD
DCLK Falling to BUSY Rising
200
ns
t
BDV
CS Falling to BUSY Enabled
200
ns
t
BTR
CS Rising to BUSY Disabled
200
ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V and
Above, T
A
= –40
°
C to +85
°
C, C
LOAD
= 50pF).
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
11
DOUT
BUSY
DIN
10
FIGURE 7. Detailed Timing Diagram.
FIGURE 8. Maximum Conversion Rate, 15-Clocks per Conversion.
1
DCLK
CS
11
DOUT
BUSY
A2
S
DIN
A1 A0
MODEDIF
PD1 PD0
10
9
8
7
6
5
4
3
2
1
0
11
10
9
8
7
6
5
4
3
2
A1 A0
15
1
15
1
A2
S
A1 A0
MODEDIF
PD1 PD0
A2
S
相關(guān)PDF資料
PDF描述
ADS7844 12-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7844E CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter 16-SO -55 to 125
ADS7844EB CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter 16-SO -55 to 125
ADS7844N 12-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7844NB CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter 16-TSSOP -55 to 125
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參數(shù)描述
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