參數(shù)資料
型號: ADS7832
英文描述: CMOS Hex Inverting Buffer/Converter 16-SOIC -55 to 125
中文描述: Autocalibrating,4通道,12位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 7/15頁
文件大?。?/td> 299K
代理商: ADS7832
7
ADS7832
PIN #
NAME
DESCRIPTION
1
SFR
Special Function Register. When connected to a microprocessor address pin, allows access to special functions
through D0 to D7. If not used, connect to DGND. This pin has an internal pull-down.
2 to 5
AIN0 to AIN3
Analog inputs. Channel 0 to channel 3.
6
V
REF
+
Positive voltage reference input. Must be
(V
A
+ 0.3V).
7
V
REF
Negative voltage reference input.
8
DGND
Digital ground. DGND = 0V.
9
V
D
Logic supply voltage. Must be
(V
A
+ 0.3V) and applied after V
A
.
10 to 17
D0 to D7
Data Bus Input/Output Pins. Normally used to read output data.
When SFR is LOW, these function as follows:
Data Bit 7 if HBE is LOW; if HBE is HIGH, acts as converter status pin and is HIGH during conversion or calibration,
goes LOW after the conversion is completed. (Acts as an inverted BUSY).
Data Bit 6 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 5 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 4 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 3 if HBE is LOW; Data Bit 11 (MSB) if HBE is HIGH.
Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH.
Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH.
Data Bit 0 (LSB) if HBE is LOW; Data Bit 8 if HBE is HIGH.
10
D7
11
12
13
14
15
16
17
D6
D5
D4
D3
D2
D1
D0
18
RD
Read Input. Active LOW; used to read the data outputs in combination with CS and HBE.
19
CS
Chip Select Input. Active LOW.
20
WR
Write Input. Active LOW; used to start a new conversion and to select an analog channel via address inputs A0 and A1
in combination with CS. The minimum WR pulse LOW width is 100ns.
21
HBE
High Byte Enable. Used to select high or low data output byte in combination with CS and RD, or to select SFR.
22
BUSY
BUSY is LOW during conversion or calibration. BUSY goes HIGH after the conversion is completed.
23
CLK
Clock Input. For internal or external clock operation. For external clock operation, connect to a 74HC-compatible
clock source. For internal clock operation, connect per the clock operation description.
24 to 25
A0 to A1
Address Inputs. Used to select one of four analog input channels in combination with CS and WR. The address inputs
are latched on the rising edge of WR or CS.
A1
A0
Selected Channel
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
AIN0
AIN1
AIN2
AIN3
26
CAL
(SHC)
Calibration Input. A calibration cycle is initiated when CAL is LOW. The minimum pulse width of CAL is 100ns. If not
used, connect to V
D
. In this case calibration is only initiated at power on, or with SFR. If D2 of the SFR is programmed
HIGH, pin 26 will be an input to control the sample-to-hold timing. A rising edge on pin 26 will switch from sample-mode
to hold-mode and initiate a conversion. This pin has an internal pull-up.
27
AGND
Analog Ground. AGND = 0V.
28
V
A
Analog Supply. Must be
(V
D
– 0.3V) and ((V
REF
+) – 0.3V)
PIN ASSIGNMENTS
相關(guān)PDF資料
PDF描述
ADS7832BN Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER
ADS7832BP Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER
ADS7833 CMOS Hex Inverting Buffer/Converter 16-SO -55 to 125
ADS7833N 10-Channel, 12-Bit DATA ACQUISITION SYSTEM
ADS7834 12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS7832BN 制造商:Rochester Electronics LLC 功能描述:
ADS7832BP 功能描述:IC 12-BIT 4CH A/D 28-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率(每秒):3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散(最大):- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:-
ADS7833 制造商:BB 制造商全稱:BB 功能描述:10-Channel, 12-Bit DATA ACQUISITION SYSTEM
ADS7833N 制造商:Rochester Electronics LLC 功能描述:- Bulk
ADS7834 制造商:BB 制造商全稱:BB 功能描述:12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER