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參數(shù)資料
| 型號： | ADS7832 |
| 英文描述： | CMOS Hex Inverting Buffer/Converter 16-SOIC -55 to 125 |
| 中文描述： | Autocalibrating，4通道，12位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 299K |
| 代理商： | ADS7832 |
13
ADS7832
FIGURE 8. Measuring Active LOW to/from Hi-Z State.
FIGURE 9. Measuring Active HIGH to/from Hi-Z State.
As long as there is at least a 4.5V difference between V
REF
+
and V
REF
–, the absolute value of errors does not change
significantly, so that accuracy will typically be within
±
1LSB
The power supply to the reference source needs to be
considered during system design to prevent V
REF
+ from
exceeding (or overshooting) V
A
, particularly at power-on.
Also, after power-on, if the reference is not stable within
33,056 clock cycles, an additional calibration cycle may be
needed.
POWER SUPPLIES
The digital and analog power supply lines to the ADS7832
should be bypassed with 10
μ
F tantalum capacitors as close
to the part as possible. Although ADS7832 has excellent
power supply rejection, even for higher frequencies, linear
regulated power supplies are recommended.
Care should be taken to insure that V
D
does not come up
before V
A
, or permanent damage to the part may occur.
Figure 11 shows a good supply approach, powering both V
A
and V
D
from a clean linear supply, with the 10
resistor
between V
A
and V
D
insuring that V
D
comes up after V
A
.
This is also a good method to further isolate the ADS7832
from digital supplies in a system with significant switching
currents that could degrade the accuracy of conversions.
GROUNDING
To maximize accuracy of the ADS7832, the analog and
digital grounds are not connected internally. These points
should have very low impedance to avoid digital noise
feeding back into the analog ground. The V
REF
– pin is used
as the reference point for input signals, so it should be
connected directly to AGND to reduce potential noise prob-
lems.
EXTERNAL CLOCK OPERATION
The circuitry required to drive the ADS7832 clock from an
external source is shown in Figure 12a. The external clock
must provide a 0.8V max for LOW and a 3.5V min for
HIGH, with rise and fall times that do not exceed 200ns. The
duty cycle of the external clock can vary as long as the LOW
time and HIGH time are each at least 200ns wide. Synchro-
nizing the conversion clock to an external system clock is
ADS7832
Output
C
L
5V
3k
Test
Point
(a) Load Circuit
(b) From LOW to Hi-Z, C
L
= 10pF
t
FALL
90%
50%
V
D
Gnd
V
D
V
OL
10%
t
15
t
14
10%
V
D
t
RISE
10%
90%
50%
V
D
Output
Enable
Gnd
V
OL
t
13
0.8V
Output
Enable
(c) From Hi-Z to LOW, C
L
= 100pF
ADS7832
Output
C
L
3k
Test
Point
(a) Load Circuit
(b) From HIGH to Hi-Z, C
L
= 10pF
t
FALL
90%
50%
V
D
Gnd
V
OH
Gnd
90%
t
15
t
14
10%
V
OH
t
RISE
10%
90%
50%
V
D
Output
Enable
Gnd
Gnd
t
13
2.4V
Output
Enable
(c) From Hi-Z to HIGH, C
L
= 100pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS7832BN | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7832BP | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7833 | CMOS Hex Inverting Buffer/Converter 16-SO -55 to 125 |
| ADS7833N | 10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| ADS7834 | 12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7832BN | 制造商:Rochester Electronics LLC 功能描述: |
| ADS7832BP | 功能描述:IC 12-BIT 4CH A/D 28-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADS7833 | 制造商:BB 制造商全稱:BB 功能描述:10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| ADS7833N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADS7834 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER |
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