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參數(shù)資料
| 型號(hào)： | ADS7831U |
| 英文描述： | 12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 中文描述： | 12位600kHz的采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | ADS7831U |
7
ADS7831
no conversion is in progress. See the
Reading Data
section
and refer to Table I for control line functions for ‘read’ and
‘convert’ modes.
FIGURE 1. Basic Operation
CS
R/C
BUSY
OPERATION
1
↓
X
X
None. Databus in Hi-Z state.
0
1
Initiates conversion. Databus remains in
Hi-Z state.
0
↓
1
Initiates conversion. Databus enters Hi-Z
state.
0
1
↑
Conversion completed. Valid data from the
most recent conversion on the databus.
↓
1
1
Enables databus with valid data from the
most recent conversion.
↓
1
0
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is completed.
0
↑
0
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is completed.
0
0
↑
Conversion completed. Valid data from the
most recent conversion in the output register,
but the output pins D11-D0 remain tri-stated.
X
X
0
New convert commands ignored. Conversion
in progress.
Table I. Control Line Functions for ‘read’ and ‘convert’.
DESCRIPTION
Full Scale Range
ANALOG INPUT
±
2.5V
1.22mV
DIGITAL INPUT
BINARY TWO'S COMPLEMENT
Least Significant
Bit (LSB)
BINARY CODE
HEX CODE
+Full Scale
(2.5V – 1LSB)
Midscale
One LSB below
Midscale
–Full Scale
2.499V
0111 1111 1111
7FF
0V
0000 0000 0000
1111 1111 1111
000
FFF
–1.22mV
–2.5V
1000 0000 0000
800
TABLE II. Ideal Input Voltages and Output Codes.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7831
50
±2.5V
–5V
+5V
0.1μF
NC
10μF
+
0.1μF
+
10μF
Convert Pulse
40ns min
D0 (LSB)
D1
D2
D3
D6
D5
D4
D7
D8
D9
D10
D11 (MSB)
0.1μF 10μF
+
BUSY
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7831.
Taking R/C (pin 23) LOW for 40ns will initiate a conver-
sion. BUSY (pin 25) will go LOW and stay LOW until the
conversion is completed and the output registers are up-
dated. Data will be output in Binary Two’s Complement
with the MSB on D11 (pin 6). BUSY going HIGH can be
used to latch the data. All convert commands will be ignored
while BUSY is LOW.
The ADS7831 will begin tracking the input signal at the end
of the conversion. Allowing 1.66
μ
s between convert com-
mands assures accurate acquisition of a new signal.
STARTING A
CONVERSION
The combination of CS (pin 24) and R/C (pin 23) LOW for a
minimum of 40ns immediately puts the sample/hold of the
ADS7831 in the hold state and starts a conversion. BUSY (pin
25) will go LOW and stay LOW until the conversion is
completed and the internal output register has been updated. All
new convert commands during BUSY LOW will be ignored.
The ADS7831 will begin tracking the input signal at the end
of the conversion. Allowing 1.66
μ
s between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 2 and 3 for timing parameters.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If it is critical that CS or R/C initiate
the conversion, be sure the less critical input is LOW at least
10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. Note that
the parallel output will be active whenever R/C is HIGH and
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