參數(shù)資料
型號: ADS7825PB
英文描述: 4 Channel, 16-Bit Sampling CMOS A/D Converter
中文描述: 4通道,16位采樣的CMOS A / D轉換
文件頁數(shù): 14/16頁
文件大?。?/td> 342K
代理商: ADS7825PB
14
ADS7825
conversions will proceed through each higher channel, cy-
cling back to zero after Channel 3.
If PWRD is held HIGH for a significant period of time, the
REF (pin 7) bypass capacitor may discharge (if the internal
reference is being utilized) and the CAP (pin 6) bypass
capacitor will discharge (for both internal and external
references). The continuous conversion mode should not be
enabled until the bypass capacitor(s) have recharged and
stabilized (1ms for 2.2
μ
F capacitors recommended). In
addition, the continuous conversion mode should not be
enabled even with a short pulse on PWRD until the mini-
mum acquisition time has been met.
MANUAL CHANNEL SELECTION (CONTC= 0V)
The channels of the ADS7825 can be selected manually by
using the A0 and A1 address pins (pins 19 and 18, respec-
tively). See Table IVb for the multiplexer truth table and
Figure 8 for channel selection timing.
into the A0 and A1 registers (pins 19 and 18, respectively)
prior to CONTC being raised HIGH, becomes the first
address in the sequential continuous conversion mode (e.g.,
if Channel 1 was the last address selected then Channel 2
will follow, then Channel 3, and so on). The A0 and A1
address inputs become outputs when the device is in this
mode. When BUSY rises at the end of a conversion, A0 and
A1 will output the address of the channel that will be
converted when BUSY goes LOW at the beginning of the
next conversion. Data will be valid for the previous channel
when BUSY rises. See Table IVa and Figure 7 for channel
selection timing in continuous conversion mode.
PWRD (pin 26) can be used to reset the multiplexer address
to zero. With the ADS7825 configured for no conversion,
PWRD can be taken HIGH for a minimum of 200ns. When
PWRD returns LOW, the multiplexer address will be reset
to zero. When the continuous conversion mode is enabled,
the first conversion will be done on channel 0. Subsequent
ADS7825 TIMING AND CONTROL
FIGURE 7. Channel Addressing in Continuous Conversion Mode (CONTC HIGH, CS and R/C LOW).
FIGURE 8. Channel Addressing in Normal Conversion Mode (CONTC and CS LOW).
0
0
1
1
0
1
0
1
AIN
3
AIN
0
AIN
1
AIN
2
AIN
0
AIN
1
AIN
2
AIN
3
DATA AVAILABLE
FROM CHANNEL
CHANNEL TO BE OR
BEING CONVERTED
A1
A0
DESCRIPTION OF OPERATION
Channel being acquired or converted is output on these
address lines. Data is valid for the previous channel. These
lines are updated when BUSY rises.
TABLE IVa. A0 and A1 Outputs (CONTC HIGH).
CHANNEL SELECTED
WHEN BUSY GOES HIGH
A1
A0
DESCRIPTION OF OPERATION
0
0
1
1
0
1
0
1
AIN
0
AIN
1
AIN
2
AIN
3
TABLE IVb. A0 and A1 Inputs (CONTC LOW).
Channel to be converted during conversion 'n + 1' is latched
when conversion 'n' is initiated (BUSY goes LOW). The selected
input starts being acquired as soon as conversion 'n' is done
(BUSY goes HIGH).
R/C
BUSY
A0, A1
(Input)
D7-D0
n – 3
n – 2
n – 1
n
n + 1
n + 2
n + 3
n – 1
n
n + 1
n + 2
n + 3
n + 4
n + 5
n + 4
n + 3
n + 2
n + 1
n
n – 1
n – 2
n + 4
Conversion Currently in Progress:
Channel Address for Conversion:
Results from Conversion:
t
30
BUSY
A0, A1
(Output)
D7-D0
n – 3
n – 2
n – 1
n
n + 1
n + 2
n + 3
n – 2
n – 1
n
n + 1
n + 2
n + 3
n + 4
n + 4
n + 3
n + 2
n + 1
n
n – 1
n – 2
n + 5
n + 4
Conversion Currently in Progress:
Channel Address for Conversion:
Results from Conversion:
t
29
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