- 您現在的位置：買賣IC網 > PDF目錄364641 > ADS7825PB 4 Channel, 16-Bit Sampling CMOS A/D Converter PDF資料下載
參數資料
| 型號： | ADS7825PB |
| 英文描述： | 4 Channel, 16-Bit Sampling CMOS A/D Converter |
| 中文描述： | 4通道，16位采樣的CMOS A / D轉換 |
| 文件頁數： | 12/16頁 |
| 文件大小： | 342K |
| 代理商： | ADS7825PB |
12
ADS7825
after the start of conversion ‘n’. Do not attempt to read data
beyond 12
μ
s after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table II and Figures 2 and 3 for timing constraints.
SERIAL OUTPUT
When PAR/SER (pin 20) is LOW, data can be clocked out
serially with the internal data clock or an external data clock.
When EXT/INT (pin 12) is LOW, DATACLK (pin 15) is an
output and is always active regardless of the state of CS (pin
23) and R/C (pin 22). The SDATA output is active when
BUSY (pin 24) is LOW. Otherwise, it is in a tri-state
condition. When EXT/INT is HIGH, DATACLK is an input.
The SDATA output is active when CS is LOW and R/C is
HIGH. Otherwise, it is in a tri-state condition. Regardless of
the state of EXT/INT, SYNC (pin 13) is an output and always
active, while TAG (pin 17) is always an input.
INTERNAL DATA CLOCK (During A Conversion)
To use the internal data clock, tie EXT/INT (pin 12) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7825 will output 16
bits of valid data, MSB first, from conversion ‘n – 1’ on
SDATA (pin 16), synchronized to 16 clock pulses output on
READING DATA
PARALLEL OUTPUT
To use the parallel output, tie PAR/SER (pin 20) HIGH. The
parallel output will be active when R/C (pin 22) is HIGH and
CS (pin 23) is LOW. Any other combination of CS and R/C
will tri-state the parallel output. Valid conversion data can be
read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When
BYTE (pin 21) is LOW, the 8 most significant bits will be
valid with the MSB on D7. When BYTE is HIGH, the 8 least
significant bits will be valid with the LSB on D0. BYTE can
be toggled to read both bytes within one conversion cycle.
Upon initial power up, the parallel output will contain
indeterminate data.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going HIGH can be used to latch the
data. Refer to Table II and Figures 2 and 3 for timing
constraints.
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n – 1’ can be read and will be valid up to 12
μ
s
TABLE II. Conversion, Data, and Address Timing. T
A
= –40
°
C to +85
°
C.
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
7
+ t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
DESCRIPTION
Convert Pulse Width
Start of Conversion to New Data Valid
Start of Conversion to BUSY LOW
BUSY LOW
End of Conversion to BUSY HIGH
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
Bus Relinquish Time
Data Valid to BUSY HIGH
Start of Conversion to Previous Data Not Valid
Bus Access Time and BYTE Delay
Start of Conversion to DATACLK Delay
DATACLK Period
Data Valid to DATACLK HIGH
DATACLK LOW to Data Not Valid
External DATACLK Period
External DATACLK HIGH
External DATACLK LOW
CS LOW and R/C HIGH to External DATACLK HIGH (Enable Clock)
R/C to CS Setup Time
CS HIGH or R/C LOW to External DATACLK HIGH (Disable Clock)
DATACLK HIGH to SYNC HIGH
DATACLK HIGH to Valid Data
Start of Conversion to SDATA Active
End of Conversion to SDATA Tri-State
CS LOW and R/C HIGH to SDATA Active
CS HIGH or R/C LOW to SDATA Tri-State
BUSY HIGH to Address Valid
Address Valid to BUSY LOW
MIN
0.04
TYP
MAX
12
21
85
21
UNITS
μ
s
μ
s
ns
μ
s
ns
ns
μ
s
μ
s
μ
s
ns
ns
μ
s
ns
μ
s
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
90
40
20
4
21
5
25
83
10
20
12
60
20
83
1.4
1.1
75
600
20
400
100
50
40
25
10
25
15
25
35
55
83
83
83
83
20
500
相關PDF資料 |
PDF描述 |
|---|---|
| ADS7825U | CMOS Dual Complementary Pair Plus Inverter 14-TSSOP -55 to 125 |
| ADS7830 | 8-Bit, 8-Channel Sampling ANALOG-TO-DIGITAL CONVERTER with I2C⑩ Interface |
| ADS7830I | CMOS Hex Inverting Buffer/Converter 16-SOIC -55 to 125 |
| ADS7830IPWR | CMOS Hex Inverting Buffer/Converter 16-SOIC -55 to 125 |
| ADS7830IPWT | 8-Bit, 8-Channel Sampling ANALOG-TO-DIGITAL CONVERTER with I2C⑩ Interface |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADS7825PBG4 | 功能描述:模數轉換器 - ADC 4 Ch 16B Sampling CMOS ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7825PG4 | 功能描述:模數轉換器 - ADC 4 Channel 16-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7825U | 功能描述:模數轉換器 - ADC 4 Channel 16-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7825U | 制造商:BURR-BROWN 功能描述:16BIT ADC 4CH SMD 7825 SOIC28 |
| ADS7825U/1K | 功能描述:模數轉換器 - ADC 4 Channel 16-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復。