參數(shù)資料
型號(hào)： ADS7815U/1K
廠商： Texas Instruments
文件頁(yè)數(shù)： 13/16頁(yè)
文件大小： 0K
描述： IC 16BIT 250KHZ A/D CONV 28SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 250mW
電壓電源： 雙 ±
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，雙極
ADS7815
6
SBAS065B
www.ti.com
TIMING
The timing shown in Figure 2 and Table II is the recom-
mended method of operating the ADS7815. The falling edge
of CS initiates the conversion. During the conversion, the
digital outputs are tri-stated and BUSY is LOW. Near the
end of the conversion, the digital outputs become active with
the most recent conversion result. After a brief delay (see
time t11 in Figure 2 and Table II), BUSY rises. The rising
edge of BUSY is used to latch the digital result in Figure 1.
R/C AND CS
The R/C (read/convert) and CS signals control the start of
conversion and, when a conversion is not in progress, the
status of the digital outputs D15 through D0. It is possible to
start a conversion by taking CS LOW and then taking R/C
LOW. However, this is not recommended and will result in
a significant decrease in signal-to-noise ratio. This is due to
FIGURE 3. Bus Timing.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
CS to R/C Delay
200
ns
t2
CS to BUSY Delay
40
ns
t3
Aperture Delay
40
ns
t4
BUSY LOW
3.3
s
t5
R/C LOW to CS LOW
100
ns
t6
BUSY HIGH to CS HIGH
250
ns
t7
Bus Access Time
10
83
ns
t8
Bus Relinquish Time
83
ns
t9
Throughput Time
4
s
t10
Conversion Time
3.3
s
t11
Data Valid to BUSY HIGH
25
35
ns
t12
CS to R/C Setup Time
40
ns
TABLE II. Conversion Timing.
FIGURE 2. ADS7815 Timing.
t
12
CS
R/C
t
7
t
8
Hi-Z State
D15 - D0
Hi-Z State
MODE
Acquire
DataValid
CS
t
9
t
6
t
5
BUSY
t
4
R/C
t
1
t
2
Hi-Z State
D15 - D0
t
11
t
8
Hi-Z State
Acquire
MODE
Convert
t
10
t
3
Acquire
DataValid
the digital outputs tri-stating while the sample and hold
transitions to the hold mode. The change in digital outputs
results in noise being coupled onto the hold capacitor.
If a conversion is not in progress or is just about to finish, the
digital outputs will be active when R/C is HIGH and CS is
LOW. This is shown in Figure 2 and Figure 3. It is possible
to return CS HIGH during the initial part of the conversion
(as is done with R/C) and prevent the digital outputs from
becoming active. At a later time, the digital results could be
read by taking CS LOW. It is also possible to leave R/C
LOW, take CS HIGH during the conversion, and read the
results at a later time by taking R/C HIGH and CS LOW.
Following a conversion, if R/C and CS are both LOW 250ns
after BUSY rises, then a new conversion will be initiated
without allowing the proper acquisition period for the sample
and hold. R/C must remain HIGH or CS must be taken
HIGH within 250ns of BUSY rising.
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