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參數(shù)資料
| 型號： | ADS7815U/1K |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 16BIT 250KHZ A/D CONV 28SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 250mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
ADS7815
4
SBAS065B
www.ti.com
PIN #
NAME
DESCRIPTION
1VIN
Analog Input. Full-scale input range is
±2.5V.
2
GND
Ground.
3
REF
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In
both cases, connect to ground with a 0.1
F ceramic capacitor in parallel with 2.2F tantalum capacitor.
4
CAP
Reference compensation capacitor. Use a parallel combination of a 0.1
F ceramic capacitor and a 2.2F tantalum capacitor.
5
GND
Ground.
6
D15 (MSB)
Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, when R/C is LOW or when a
conversion is in progress.
7
D14
Data Bit 14. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
8
D13
Data Bit 13. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
9
D12
Data Bit 12. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
10
D11
Data Bit 11. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
11
D10
Data Bit 10. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
12
D9
Data Bit 9. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
13
D8
Data Bit 8. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
14
GND
Ground.
15
D7
Data Bit 7. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
16
D6
Data Bit 6. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
17
D5
Data Bit 5. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
18
D4
Data Bit 4. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
19
D3
Data Bit 3. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
20
D2
Data Bit 2. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
21
D1
Data Bit 1. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
22
D0 (LSB)
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, when R/C is LOW or when a
conversion is in progress.
23
–VS
Negative supply input. Nominally –5V. Decouple to analog ground with 0.1
F ceramic and 10F tantalum capacitors.
24
R/C
Read/convert input. With R/C HIGH, CS going LOW will enable the output data bits if a conversion is not in progress. With
R/C LOW, CS going LOW will start a conversion if one is not already in progress.
25
CS
Chip select. With R/C LOW, CS going LOW will initiate a conversion if one is not already in progress. With R/C HIGH, CS
going LOW will enable the output data bits if a conversion is not in progress.
26
BUSY
Busy output. Falls when a conversion is started, and remains LOW until the conversion is completed. With CS LOW and
R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to latch the data. CS or R/C must
be HIGH within 250ns after BUSY rises or another conversion will start without time for signal acquisition.
27
+VS
Positive supply input. Nominally +5V. Connect directly to pin 28.
28
+VS
Positive supply input. Nominally +5V. Connect directly to pin 27. Decouple to ground with 0.1
F ceramic and 10F
tantalum capacitors.
TABLE I. Pin Assignments.
PIN CONFIGURATION
Top View
SOIC
+V
S
+V
S
BUSY
CS
R/C
–V
S
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
V
IN
GND
REF
CAP
GND
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7815
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