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參數(shù)資料
| 型號： | ADS7812UBG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SER 40K 16SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Basics |
| 標準包裝： | 40 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 35mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 3 個單端，單極；3 個單端，雙極 |
ADS7812
9
SBAS042A
www.ti.com
BINARY TWO’S COMPLEMENT
DIGITAL OUTPUT
TABLE III. Ideal Input Voltage and Corresponding Digital Output for Two Common Input Ranges.
DESCRIPTION
ANALOG INPUT
Full-Scale Range
±10V
0.5V to 4.5V
Least Significant Bit (LSB)
4.88mV
0.98mV
BINARY CODE
HEX CODE
+Full Scale –1LSB
9.99512V
4.49902V
0111 1111 1111
7FF
Midscale
0V
2.5V
0000 0000 0000
000
Midscale –1LSB
–4.88mV
2.49902 V
1111 1111 1111
FFF
–Full Scale
–10V
0.5V
1000 0000 0000
800
FIGURE 3. Block Diagram of the ADS7812’s Digital Inputs and Outputs.
READING DATA
The ADS7812’s digital output is in Binary Two’s Comple-
ment (BTC) format. Table III shows the relationship be-
tween the digital output word and the analog input voltage
under ideal conditions.
Figure 3 shows the relationship between the various digital
inputs, digital outputs, and internal logic of the ADS7812.
Figure 4 shows when the internal shift register of the
ADS7812 is updated and how this relates to a single conver-
sion cycle. Together, these two figures point out a very
important aspect of the ADS7812: the conversion result is
not available until after the conversion is complete. The
implications of this are discussed in the following sections.
FIGURE 4. Timing of the Shift Register Update.
Q
D
S0
Q
Update of the shift
register occurs just prior
to BUSY Rising(1)
D
S1
Q
D
S2
Q
D
S10
Q
D
S11
Q
Shift Register
Working Register
Converter Core
D
SOUT
Q
D
W0
Q
Each flip-flop in the
working register is
latched as the
conversion proceeds
D
W1
Q
D
W2
Q
D
W10
Q
D
W11
Delay
DATA
BUSY
DATACLK
CDAC
Control Logic
Clock
REF
EXT/INT
CONV
CS
NOTE: (1) If EXT/INT is HIGH (external clock), DATACLK is HIGH, and CS is LOW
during this time, the shift register will not be updated and the conversion result will be lost.
CONV
t
6 – t25
t
25
BUSY
NOTE: Update of the internal shift register occurs in the
shaded region. If EXT/INT is HIGH, then DATACLK
must be LOW or CS must be HIGH during this time.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7812UE4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power Serial 12-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7812UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Pwr Serial 12B Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7813 | 制造商:BB 制造商全稱:BB 功能描述:Low-Power, Serial 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7813P | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power Serial 16-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7813P | 制造商:Texas Instruments 功能描述:16BIT ADC SERIAL O/P 7813 PDIP16 |
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