參數(shù)資料
型號: ADS62P44IRGCTG4
廠商: Texas Instruments
文件頁數(shù): 18/78頁
文件大小: 0K
描述: IC ADC 14BIT SER/PAR 105M 64VQFN
產(chǎn)品培訓模塊: Data Converter Basics
標準包裝: 250
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
Table 15.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
17
0
<FINE GAIN> 0 to 6 dB gain in 0.5 dB steps
D2
–D0
<FINE GAIN> Gain programmability in 0.5 dB steps
0000
0 dB gain, default after reset
0001
0.5 dB gain
0010
1.0 dB gain
0011
1.5 dB gain
0100
2.0 dB gain
0101
2.5 dB gain
0110
3.0 dB gain
0111
3.5 dB gain
1000
4.0 dB gain
1001
4.5 dB gain
1010
5.0 dB gain
1011
5.5 dB gain
1100
6.0 dB gain
Others
Unused
Table 16.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
18
<CUSTOM LOW> Lower 8 bits
19
0
<CUSTOM HIGH> Upper 6 bits
D7-D0
<CUSTOM LOW>
8 lower bits of custom pattern available at the output instead of ADC data.
D5-D0
<CUSTOM HIGH>
6 upper bits of custom pattern available at the output instead of ADC data.
Copyright
2007–2012, Texas Instruments Incorporated
25
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