參數(shù)資料
型號(hào): ADS62P43IRGC25
廠商: Texas Instruments
文件頁(yè)數(shù): 8/78頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14B SER/PAR 80MSPS 64VQFN
標(biāo)準(zhǔn)包裝: 25
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be
loaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits the register data. The interface can work with
SCLK frequency from 20 MHz down to low speeds (few Hertz), and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to their default values. This can be done in one of two
ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as
shown in Figure 6.
OR
2. By applying software reset. Using the serial interface, set the
<RST> bit to high. This initializes internal
registers to their default values and then self-resets the
<RST> bit to low. In this case the RESET pin is kept
low.
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25
°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V,
DRVDD = 1.8 V to 3.3 V, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNIT
fSCLK
SCLK frequency
> DC
20
MHz
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDS
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
16
Copyright
2007–2012, Texas Instruments Incorporated
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