參數(shù)資料
型號: ADS62P43IRGC25
廠商: Texas Instruments
文件頁數(shù): 19/78頁
文件大?。?/td> 0K
描述: IC ADC 14B SER/PAR 80MSPS 64VQFN
標準包裝: 25
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應商設備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
Table 17.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
<OFFSET TC>
<GAIN CORRECTION>
1A
<LOW LATENCY>
Offset correction time constant
0 to 0.5 dB, steps of 0.05 dB
D2
–D0
0000
0 dB gain, default after reset
0001
+0.5 dB gain
0010
+0.10 dB gain
0011
+0.15 dB gain
0100
+0.20 dB gain
0101
+0.25 dB gain
0110
+0.30 dB gain
0111
+0.35 dB gain
1000
+0.40 dB gain
1001
+0.45 dB gain
1010
+0.5 dB gain
D6-D4
<OFFSET TC> Time constant of offset correction in number of clock cycles (seconds, for sampling frequency = 125
MSPS)
000
227 (1.1 s)
001
226 (0.55 s)
010
225 (0.27 s)
011
224 (0.13 s)
100
228 (2.15 s)
101
229 (4.3 s)
110
227 (1.1 s)
111
227 (1.1 s)
D7
<LOW LATENCY>
0
Default latency, 14 clock cycles
1
Low latency enabled, 10 clock cycles
– Digital Processing Block is bypassed.
Table 18.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
<FILTER COEFF
<OFFSET Enable>
SELECT
>
<FILTER Enable>
<DECIMATION RATE>
<ODD TAP
1B
Offset correction
0
Enable
>
In-built or custom
Enable digital filtering
Decimate by 2,4,8
enable
coefficients
26
Copyright
2007–2012, Texas Instruments Incorporated
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