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| 型號： | ADS6243IRGZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, QFN-48 |
| 文件頁數(shù)： | 57/76頁 |
| 文件大?。?/td> | 3497K |
| 代理商： | ADS6243IRGZT |
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CAPTURE TEST PATTERNS
SLAS542A – MAY 2007 – REVISED JULY 2007
ADS624X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended
to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures
sufficient setup/hold times for a reliable capture by the receiver.
The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the
receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between
DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is
aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface,
the SYNC pattern is 7 '1's followed by 7 '0's (from MSB to LSB). This information can be used by the receiver
logic to shift the deserialized data till it matches the SYNC pattern.
In addition to DESKEW and SYNC, the ADS624X includes other test patterns to verify correctness of the capture
by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines
simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization
and bit order.
Table 26. Test Patterns
PATTERN
DESCRIPTION
All zeros
Outputs logic low.
All ones
Outputs logic high.
Toggle
Outputs toggle pattern - <D13-D0> alternates between 10101010101010 and 01010101010101 every clock cycle.
Outputs a 14-bit custom pattern. The 14-bit custom pattern can be specified into two serial interface registers. In the 2-wire
Custom
interface, each code is sent over the 2 wires depending on the serialization and bit order.
Sync
Outputs a sync pattern.
Deskew
Outputs deskew pattern. Either <D13-D0> = 10101010101010 OR <D11-D0> = 01010101010101 every clock cycle.
Table 27. SYNC Pattern
INTERFACE OPTION
SERIALIZATION
SYNC PATTERN ON EACH WIRE
14 X
MSB-11111110000000-LSB
1-Wire
16 X
MSB-111111111000000000-LSB
14 X
MSB-1111000-LSB
2-Wire
16 X
MSB-11110000-LSB
60
Copyright 2007, Texas Instruments Incorporated
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