- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364640 > ADS574JP Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER PDF資料下載
參數(shù)資料
| 型號： | ADS574JP |
| 英文描述： | Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 微處理器兼容采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 413K |
| 代理商： | ADS574JP |
7
ADS574
Conversion is initiated by a HIGH-to-LOW transition of
R/C. The three-state data output buffers are enabled when
R/C is HIGH and STATUS is LOW. Thus, there are two
possible modes of operation; data can be read with either a
positive pulse on R/C, or a negative pulse on STATUS. In
either case the R/C pulse must remain LOW for a minimum
of 25ns.
Figure 3 illustrates timing with an R/C pulse which goes
LOW and returns HIGH during the conversion. In this case,
the three-state outputs go to the high-impedance state in
response to the falling edge of R/C and are enabled for
external access of the data after completion of the conver-
sion.
Figure 4 illustrates the timing when a positive R/C pulse is
used. In this mode the output data from the previous conver-
sion is enabled during the time R/C is HIGH. A new
conversion is started on the falling edge of R/C, and the
three-state outputs return to the high-impedance state until
the next occurrence of a HIGH R/C pulse. Timing specifica-
tions for stand-alone operation are listed in Table IV.
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the A
0
input, which is latched upon receipt of a conver-
sion start transition (described below). If A
0
is latched
HIGH, the conversion continues for 8 bits. The full 12-bit
conversion will occur if A
0
is LOW. If all 12 bits are read
following an 8-bit conversion, the 4LSBs (DB0-DB3) will
be LOW (logic 0). A
0
is latched because it is also involved
in enabling the output buffers. No other control inputs are
latched.
FIGURE 2. Basic
±
10V Operation.
CONVERSION START
The converter initiates a conversion based on a transition
occurring on any of three logic inputs (CE, CS, and R/C) as
shown in Table III. Conversion is initiated by the last of the
three to reach the required state and thus all three may be
dynamically controlled. If necessary, all three may change
state simultaneously, and the nominal delay time is the same
regardless of which input actually starts the conversion. If it
is desired that a particular input establish the actual start of
conversion, the other two should be stable a minimum of
50ns prior to the transition of the critical input. Timing
relationships for start of conversion timing are illustrated in
Figure 5. The specifications for timing are contained in
Table V.
The STATUS output indicates the current state of the con-
verter by being in a high state only during conversion.
During this time the three state output buffers remain in a
high-impedance state, and therefore data cannot be read
during conversion. During this period additional transitions
of the three digital inputs which control conversion will be
ignored, so that conversion cannot be prematurely termi-
nated or restarted. However, if A
0
changes state after the
beginning of conversion, any additional start conversion
transition will latch the new state of A
0
, possibly resulting in
an incorrect conversion length (8 bits vs 12 bits) for that
conversion.
Bit 11 (MSB)
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Status
Output
Convert Command
ADS574
+5V
10μF
(1)
NC*
50
50
+5V
Leave Unconnected
*Not internally connected
NOTE: (1) Connect to ground or V
for
emulation. Connect to +5 for control mode.
±10V
Analog
Input
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS574JU | Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER |
| ADS574JE | Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER |
| ADS574KE | Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER |
| ADS574KP | Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER |
| ADS574KU | Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS574JPG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Mcrprcsr-Compatible Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS574JU | 制造商: 功能描述: 制造商:undefined 功能描述: |
| ADS574KE | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Mcrprcsr-Compatible Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS574KE | 制造商:Texas Instruments 功能描述:IC 12BIT ADC CMOS PDIP28 574 |
| ADS574KEG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Microproc-Comp Sampling CMOS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復。