參數(shù)資料
型號(hào)： ADS5500
英文描述： 14-Bit, 80MSPS Analog-to-Digital Converter
中文描述： 14位，80Msps模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 7/30頁(yè)
文件大小： 401K
代理商： ADS5500
SBAS308A MAY 2004 REVISED MARCH 2005
www.ti.com
7
RESET TIMING CHARACTERISTICS
Typical values at T
A
= +25
°
C, full temperature range is T
MIN
= 40
°
C to T
MAX
= +85
°
C, AV
DD
= DRV
DD
= 3.3V, and 3V
PP
differential clock, unless
otherwise noted.
PARAMETER
Switching Specification
DESCRIPTION
MIN
TYP
MAX
UNIT
Power-on delay, t
1
Delay from poweron of AV
DD
and DRV
DD
to
RESET pulse active
Pulse width of active RESET signal
Delay from RESET disable to SEN active
10
ms
Reset pulse width, t
2
Register write delay, t
3
2
2
μ
s
μ
s
RESET (Pin 35)
t
1
≥
10ms
t
2
≥
2
μ
s
t
3
≥
2
μ
s
SEN Active
Power Supply
(AVDD, DRVDD)
Figure 2. Reset Timing Diagram
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK
when SEN is active.
Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
Minimum width of data stream for a valid loading is
16 clocks.
Data is loaded at every 16th SCLK falling edge
while SEN is low.
In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
A3
ADDRESS
SDATA
MSB
DATA
A2
A1
A0
D11
D10
D9
D0
Figure 3. DATA Communication is 2-Byte, MSB First
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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