參數(shù)資料
型號(hào): ADS5500
英文描述: 14-Bit, 80MSPS Analog-to-Digital Converter
中文描述: 14位,80Msps模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 26/30頁(yè)
文件大?。?/td> 401K
代理商: ADS5500
SBAS308A MAY 2004 REVISED MARCH 2005
www.ti.com
26
rate described in the timing diagram of Figure 1. Care
should be taken to ensure that all output lines (including
CLKOUT) have nearly the same load as D2 (pin 51).
This circuit also reduces the sensitivity of the output
timing versus supply voltage or temperature. Placing
external resistors in series with the outputs is
not
recommended.
The timing characteristics of the digital outputs change
for sampling rates below the 80MSPS maximum
sampling frequency. Table 5 shows the timing
parameters for sampling rates of 20MSPS, 40MSPS,
and 65MSPS.
To use the input clock as the data capture clock, it is
necessary to delay the input clock by a delay, t
d
, that
results in the desired setup or hold time. Use either of
the following equations to calculate the value of t
d
.
Desired setup time = t
d
t
START
Desired hold time = t
END
t
d
SERIAL PROGRAMMING INTERFACE
The ADS5542 has internal registers that enable the
programming of the device into modes as described in
previous sections. Programming is done through a
3-wire serial interface. The timing diagram and register
settings in the
Serial Programming Interface
section
describe the use of this interface.
Table 2 shows the different modes and the bit values to
be written to the register to enable them.
The ADS5542 internal registers default to all zeros on
reset. The device is reset by applying a high pulse on
the RESET pin (pin 35) for a minimum of 2
μ
s at least
10ms after both the AV
DD
and DRV
DD
power supplies
have come up (as illustrated in Figure 2) In reset, the
ADC outputs are forced low. Note that the RESET pin
has a 200k
pull-up resistor to AV
DD
.
If the ADS5542 is to be used solely in the default mode
set at reset, the serial interface pins can be tied to fixed
voltages. In this case, tie SCLK high, SEN low, and
SDATA to either a high or low voltage.
PowerPAD Package
The PowerPAD package is a thermally-enhanced
standard size IC package designed to eliminate the use
of bulky heatsinks and slugs traditionally used in
thermal packages. This package can be easily mounted
using standard PCB assembly techniques, and can be
removed and replaced using standard repair
procedures.
The PowerPAD package is designed so that the
leadframe die pad (or thermal pad) is exposed on the
bottom of the IC. This provides an extremely low
thermal resistance path between the die and the
exterior of the package. The thermal pad on the bottom
of the IC can then be soldered directly to the PCB, using
the PCB as a heatsink.
Table 5. Timing Characteristics at Additional Sampling Frequencies
f
S
(MSPS)
t
SETUP
(ns)
MIN
TYP
t
HOLD
(ns)
TYP
t
START
(ns)
TYP
t
END
(ns)
TYP
t
RISE
(ns)
TYP
t
FALL
(ns)
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
65
4.3
5.7
2
3
2.8
4.5
8.3
11.8
6.6
7.2
5.5
6.4
40
8.5
11.0
2.6
3.5
1
1.5
8.9
14.5
7.5
8
7.3
7.8
20
17.0
25.7
2.5
4.7
9.8
2
9.5
21.6
7.5
8
7.6
8
相關(guān)PDF資料
PDF描述
ADS5521 14-Bit, 80MSPS Analog-to-Digital Converter
ADS5522 14-Bit, 80MSPS Analog-to-Digital Converter
ADS5541 MOSFET, N SC-75AMOSFET, N SC-75A; Transistor type:MOSFET; Transistor polarity:N; Voltage, Vds max:20V; Case style:SC-75A; Current, Id cont:0.14A; Current, Idm pulse:0.5A; Power, Pd:0.25W; Resistance, Rds on:10R; SMD:1; Depth,
ADS5542 14-Bit, 80MSPS Analog-to-Digital Converter
ADS5520 14-Bit, 80MSPS Analog-to-Digital Converter
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