參數(shù)資料
型號(hào): ADS1271IPWR
元件分類: ADC
英文描述: 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER
中文描述: 24位寬帶模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù): 7/29頁(yè)
文件大?。?/td> 381K
代理商: ADS1271IPWR
SBAS306A NOVEMBER 2004 REVISED DECEMBER 2004
www.ti.com
7
TIMING CHARACTERISTICS: FRAME-SYNC FORMAT
SCLK
FSYNC
DOUT
DIN
t
DOHD
t
FPW
t
S
t
SF
t
SPW
t
SPW
t
FRAME
t
FPW
t
FS
t
SPW
t
DIHD
t
DDO
t
DIST
Bit 23 (MSB)
Bit 22
Bit 21
t
DOPD
CLK
t
CPW
t
CPW
t
CF
τ
C
TIMING REQUIREMENTS: FRAME-SYNC FORMAT
for TA = 40
°
C to +105
°
C and DVDD = 1.65V to 3.6V.
SYMBOL
PARAMETER
tCLK
CLK period (1/fCLK)
tCPW
CLK positive or negative pulse width
tCS
Rising edge of CLK to falling edge of SCLK
MIN
37
TYP
MAX
1000
UNIT
ns
15
ns
2
8
ns
High-Speed mode
256
CLK periods
tFRAME
Frame period (1/fDATA)
High-Resolution mode
256 or 512(1)
256 or 512(1)
CLK periods
Low-Power mode
CLK periods
tFPW
tFS
tSF
FSYNC positive or negative pulse width
1
SCLK periods
Rising edge of FSYNC to rising edge of SCLK
5
ns
Rising edge of SCLK to rising edge of FSYNC
5
ns
SCLK period (SCLK must
be continuously running)
High-Speed mode
τ
FRAME/64
τ
FRAME/128
τ
FRAME/64
τ
FRAME periods
τ
FRAME periods
τ
FRAME periods
ns
τ
S
High-Resolution mode
Low-Power mode
tSPW
tDOHD(2)
tDOPD(2)
tDDO(2)
tDIST
tDIHD
(1)The ADS1271 automatically detects either frame period.
(2)Load on DOUT = 20pF.
SCLK positive or negative pulse width
0.4
τ
SCLK
0.6
τ
SCLK
SCLK falling edge to old DOUT invalid (hold time)
5
ns
SCLK falling edge to new DOUT valid (propagation delay)
12
ns
Valid DOUT to falling edge of FSYNC
0
ns
New DIN valid to falling edge of SCLK (setup time)
6
ns
Old DIN valid to falling edge of SCLK (hold time)
6
ns
相關(guān)PDF資料
PDF描述
ADS1271EVM-PDK modular EVM form factor
ADS1271EVM modular EVM form factor
ADS1601 16-BIT 1.25MSPS ANALOG TO DIGITAL CONVERTER
ADS1601IPFBR 16-BIT 1.25MSPS ANALOG TO DIGITAL CONVERTER
ADS1601IPFBT 16-BIT 1.25MSPS ANALOG TO DIGITAL CONVERTER
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