參數(shù)資料
型號: ADS1271IPW
元件分類: ADC
英文描述: 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER
中文描述: 24位寬帶模數(shù)轉換器
文件頁數(shù): 14/29頁
文件大小: 381K
代理商: ADS1271IPW
SBAS306A NOVEMBER 2004 REVISED DECEMBER 2004
www.ti.com
14
OVERVIEW
The ADS1271 is a 24-bit, delta-sigma ADC. It offers the
combination of outstanding DC accuracy and superior AC
performance. Figure 37 shows the block diagram for the
ADS1271. The ADS1271 converter is comprised of an
advanced, 6th-order, chopper-stabilized, delta-sigma
modulator followed by a low-ripple, linear phase FIR filter.
The modulator measures the differential input signal,
V
IN
= (AINP – AINN), against the differential reference,
V
REF
= (VREFP – VREFN). The digital filter receives the
modulator signal and provides a low-noise digital output.
To allow tradeoffs among speed, resolution, and power,
three modes of operation are supported on the ADS1271:
High-Speed, High-Resolution, and Low-Power. Table 1
summarizes
In High-Speed mode, the data rate is 105kSPS; in
High-Resolution mode, the SNR = 109dB; and in
Low-Power mode, the power dissipation is only 35mW.
the
performance
of
each
mode.
The ADS1271 is configured by simply setting the
appropriate IO pins—there are no registers to program.
Data is retrieved over a serial interface that supports both
SPI and Frame-Sync formats. The ADS1271 has a
daisy-chainable output and the ability to synchronize
externally, so it can be used conveniently in multichannel
systems.
Σ
Modulator
Digital
Filter
VREFP
V
REF
V
IN
VREFN
Σ
Σ
DRDY/FSYNC
SCLK
DOUT
DIN
FORMAT
SYNC/PDWN
MODE
CLK
SPI
or
Frame
Sync
Serial
Interface
AINP
AINN
Figure 37. Block Diagram
Table 1. Operating Mode Performance Summary
MODE
DATA RATE (SPS)
PASSBAND (Hz)
SNR (dB)
NOISE (
μ
VRMS)
9.0
POWER (mW)
High-Speed
105,469
47,777
106
92
High-Resolution
52,734
23,889
109
6.5
90
Low-Power
52,734
23,889
106
9.0
35
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參數(shù)描述
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