參數(shù)資料
型號(hào)： ADS1256IDBT
英文描述： Very Low Noise, 24-Bit Analog-to-Digital Converter
中文描述： 極低噪聲，24位模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 25/39頁(yè)
文件大?。?/td> 427K
代理商： ADS1256IDBT
SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
25
Self-Calibration
Self-calibration corrects internal offset and gain errors.
During self-calibration, the appropriate calibration signals
are applied internally to the analog inputs.
SELFOCAL performs a self offset calibration. The analog
inputs AIN
P
and AIN
N
are disconnected from the signal
source and connected to AVDD/2. See Table 19 for the
time required for self offset calibration for the different data
rate settings. As with most of the ADS1255/6 timings, the
calibration time scales directly with f
CLKIN
. Self offset
calibration updates the OFC register.
Table 19. Self Offset and System Offset
Calibration Timing
DATA RATE
(SPS)
30,000
SELF OFFSET CALIBRATION AND
SYSTEM OFFSET CALIBRATION TIME
387
μ
s
453
μ
s
587
μ
s
853
μ
s
1.3ms
15,000
7500
3750
2000
1000
2.3ms
500
4.3ms
100
20.3ms
60
33.7ms
50
40.3ms
30
67.0ms
25
80.3ms
15
133.7ms
10
200.3ms
5
400.3ms
2.5
800.3ms
NOTE: For fCLKIN = 7.68MHz.
SELFGCAL performs a self gain calibration. The analog
inputs AIN
P
and AIN
N
are disconnected from the signal
source and AIN
P
is connected internally to VREFP while
AIN
N
is connected to VREFN. Self gain calibration can be
used with any PGA setting, and the ADS1255/6 has
excellent gain calibration even for the higher PGA settings,
as shown in the Typical Characteristics section. Using the
buffer will limit the common-mode range of the reference
inputs during self gain calibration since they will be
connected to the buffer inputs and must be within the
specified analog input range. When the voltage on VREFP
or VREFN exceeds the buffer analog input range
(AVDD – 2.0V), the buffer must be turned off during self
gain calibration. Otherwise, use system gain calibration or
write the gain coefficients directly to the FSC register.
Table 20 shows the time required for self gain calibration
for the different data rate and PGA settings. Self gain
calibration updates the FSC register.
Table 20. Self Gain Calibration Timing
DATA RATE
(SPS)
30,000
15,000
7500
3750
2000
1000
500
100
60
50
30
25
15
10
5
2.5
PGA SETTING
4
451
μ
s
484
μ
s
617
μ
s
884
1.4ms
2.4ms
4.5ms
21.0ms
34.1ms
41.7ms
67.8ms
83.0ms
135.3ms
207.0ms
413.7ms
827.0ms
1
2
8
16, 32, 64
651
μ
s
551
μ
s
751
μ
s
417
μ
s
484
μ
s
617
μ
s
417
μ
s
484
μ
s
617
μ
s
517
μ
s
551
μ
s
617
μ
s
NOTE: For fCLKIN = 7.68MHz.
SELFCAL performs first a self offset and then a self gain
calibration. The analog inputs are disconnected from the
from the signal source during self-calibration. When using
the input buffer with self-calibration, make sure to observe
the common-mode range of the reference inputs as
described above. Table 21 shows the time required for
self-calibration for the different data rate settings.
Self-calibration updates both the OFC and FSC registers.
Table 21. Self-Calibration Timing
DATA RATE
(SPS)
30,000
15,000
7500
3750
2000
1000
500
100
60
50
30
25
15
10
5
2.5
PGA SETTING
4
692
μ
s
696
μ
s
896
μ
s
1.3ms
2.0ms
3.6ms
6.6ms
31.2ms
50.9ms
61.8ms
101.3ms
123.2ms
202.1ms
307.2ms
613.8ms
1227.2ms
1
2
8
16, 32, 64
892
μ
s
896
μ
s
1029
μ
s
596
μ
s
696
μ
s
896
μ
s
596
μ
s
696
μ
s
896
μ
s
696
μ
s
762
μ
s
896
μ
s
NOTE: For fCLKIN = 7.68MHz.
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