參數(shù)資料
型號(hào)： ADS1256IDBT
英文描述： Very Low Noise, 24-Bit Analog-to-Digital Converter
中文描述： 極低噪聲，24位模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 23/39頁(yè)
文件大小： 427K
代理商： ADS1256IDBT
SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
23
DATA FORMAT
The ADS1255/6 output 24 bits of data in Binary Two’s
Complement format. The LSB has a weight of
2V
REF
/(PGA(2
23
1)). A positive full-scale input produces
an output code of 7FFFFFh and the negative full-scale
input produces an output code of 800000h. The output
clips at these codes for signals exceeding full-scale.
Table 16 summarizes the ideal output codes for different
input signals.
Table 16. Ideal Output Code vs Input Signal
INPUT SIGNAL VIN
(AINP AINN)
IDEAL OUTPUT CODE(1)
2V
REF
PGA
7FFFFFh
2V
REF
PGA
(
2
23
1
)
000001h
0
000000h
2V
REF
PGA
(
2
23
1
)
FFFFFFh
2V
REF
PGA
2
23
2
23
1
800000h
(1)Excludes effects of noise, INL, offset, and gain errors.
GENERAL-PURPOSE DIGITAL I/O (D0-D3)
The ADS1256 has 4 pins dedicated for digital I/O and the
ADS1255 has 2 digital I/O pins. All of the digital I/O pins are
individually configurable as either inputs or outputs
through the IO register. The DIR bits of the IO register
define whether each pin is an input or output, and the DIO
bits control the status of the pins. Reading back the DIO
register shows the state of the digital I/O pins, whether they
are configured as inputs or outputs by the DIR bits. When
digital I/O pins are configured as inputs, the DIO register
is used to read the state of these pins. When configured as
outputs, DIO sets the output value. On the ADS1255, the
digital I/O pins D2 and D3 do not exist and the settings of
the IO register bits that control operation of D2 and D3
have no effect on that device.
During Standby and Power-Down modes, the GPIO
remain active. If configured as outputs, they continue to
drive the pins. If configured as inputs, they must be driven
(not left floating) to prevent excess power dissipation.
The digital I/O pins are set as inputs after power-up or a
reset, except for D0/CLKOUT, which is enabled as a clock
output. If the digital I/O pins are not used, either leave them
as inputs tied to ground or configure them as outputs. This
prevents excess power dissipation.
CLOCK OUTPUT (D0/CLKOUT)
The clock output pin can be used to clock another device,
such as a microcontroller. This clock can be configured to
operate at frequencies of f
CLKIN
, f
CLKIN
/2, or f
CLKIN
/4 using
CLK1 and CLK0 in the ADCON register. Note that enabling
the output clock and driving an external load will increase
the digital power dissipation. Standby mode does not
affect the clock output status. That is, if Standby is
enabled, the clock output will continue to run during
Standby mode. If the clock output function is not needed,
it should be disabled by writing to the ADCON register after
power-up or reset.
CLOCK GENERATION
The master clock source for the ADS1255/6 can be
provided using an external crystal or clock generator.
When the clock is generated using a crystal, external
capacitors must be provided to ensure start-up and a
stable clock frequency, as shown in Figure 22. Table 17
lists two recommended crystals. Long leads should be
minimized with the crystal placed close to the ADS1255/6
pins. For information on ceramic resonators, see
application note SBAA104,
Using Ceramic Resonators
with the ADS1255/6
, available for download at
www.ti.com.
C
1
Crystal
XTAL1/CLKIN
XTAL2
C
1
, C
2
: 5pF to 20pF
C
2
Figure 22. Crystal Connection
Table 17. Recommended Crystals
MANUFACTURER
FREQUENCY
PART
NUMBER
Citizen
7.68MHz
CIA/53383
ECS
8.0MHz
ECS-80-5-4
When using a crystal, neither the XTAL1/CLKIN nor
XTAL2 pins can be used to drive any other logic. If other
devices need a clock source, the D0/CLKOUT pin is
available for this function. When using an external clock
generator, supply the clock signal to XTAL1/CLKIN and
leave XTAL2 floating. Make sure the external clock
generator supplies a clean clock waveform. Overshoot
and glitches on the clock will degrade overall performance.
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