參數(shù)資料
型號(hào): ADS1256IDB
英文描述: Very Low Noise, 24-Bit Analog-to-Digital Converter
中文描述: 極低噪聲,24位模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 7/39頁(yè)
文件大小: 427K
代理商: ADS1256IDB
SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
7
SCLK
t
13
t
12
t
13
t
15
t
14
Figure 2. SCLK Reset Timing
TIMING CHARACTERISTICS FOR FIGURE 2
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
τ
CLKIN(1)
τ
CLKIN
τ
CLKIN
τ
CLKIN
t12
SCLK reset pattern, first high pulse
300
500
t13
SCLK reset pattern, low pulse
5
t14
SCLK reset pattern, second high pulse
550
750
t15
SCLK reset pattern, third high pulse
1050
1250
(1)
τ
CLKIN = master clock period = 1/fCLKIN.
t
16
RESET, SYNC/PDWN
Figure 3. RESET and SYNC/PDWN Timing
TIMING CHARACTERISTICS FOR FIGURE 3
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
τ
CLKIN(1)
t16
RESET, SYNC/PDWN, pulse width
4
(1)
τ
CLKIN = master clock period = 1/fCLKIN.
DRDY
t
17
Figure 4. DRDY Update Timing
TIMING CHARACTERISTICS FOR FIGURE 4
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
τ
CLKIN(1)
t17
Conversion data invalid while being updated (DRDY shown with no data retrieval)
16
(1)
τ
CLKIN = master clock period = 1/fCLKIN.
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