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參數(shù)資料
| 型號： | ADS1256 |
| 英文描述： | Very Low Noise, 24-Bit Analog-to-Digital Converter |
| 中文描述： | 極低噪聲，24位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 18/39頁 |
| 文件大?。?/td> | 427K |
| 代理商： | ADS1256 |
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SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
18
DIGITAL FILTER
The programmable low-pass digital filter receives the
modulator output and produces a high-resolution digital
output. By adjusting the amount of filtering, tradeoffs can
be made between resolution and data rate: filter more for
higher resolution, filter less for higher data rate. The filter
is comprised of two sections, a fixed filter followed by a
programmable filter. Figure 13 shows the block diagram of
the analog modulator and digital filter. Data is supplied to
the filter from the analog modulator at a rate of f
CLKIN
/4.
The fixed filter is a 5th-order sinc filter with a decimation
value of 64 that outputs data at a rate of f
CLKIN
/256. The
second stage of the filter is a programmable averager
(1st-order sinc filter) with the number of averages set by
the DRATE register. The data rate is a function of the
number of averages (Num_Ave) and is given by
Equation 1.
Data Rate
f
CLKIN
256
1
Num_Ave
Num_Ave
(set by DRATE)
Modulator Rate =
fCLKIN/4
Analog
Modulator
sinc5
Filter
Programmable
Averager
Digital Filter
DataRate
f
CLKIN
256
DataRate
f
CLKIN
256
1
Num_Ave
Figure 13. Block Diagram of the Analog
Modulator and Digital Filter
Table 11 shows the averaging and corresponding data rate
for each of the 16 valid DRATE register settings when
f
CLKIN
= 7.68MHz. Note that the data rate scales directly
with the CLKIN frequency. For example, reducing f
CLKIN
from 7.68MHz to 3.84MHz reduces the data rate for
DR[7:0] = 11110000 from 30,000SPS to 15,000SPS.
Table 11. Number of Averages and Data Rate for
Each Valid DRATE Register Setting
DRATE
DR[7:0]
NUMBER OF AVERAGES FOR
PROGRAMMABLE FILTER
(Num_Ave)
DATA RATE(1)
(SPS)
11110000
1 (averager bypassed)
30,000
11100000
2
15,000
11010000
4
7500
11000000
8
3750
10110000
15
2000
10100001
30
1000
10010010
60
500
10000010
300
100
01110010
500
60
01100011
600
50
01010011
1000
30
01000011
1200
25
00110011
2000
15
00100011
3000
10
00010011
6000
5
00000011
(1)for fCLKIN = 7.68MHz.
12,000
2.5
(1)
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| ADS1271IPWR | 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER |
| ADS1271EVM-PDK | modular EVM form factor |
| ADS1271EVM | modular EVM form factor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1256EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1256 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1256EVM-PDK | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1256 Perf Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1256IDB | 制造商:BB 制造商全稱:BB 功能描述:Very Low Noise, 24-Bit Analog-to-Digital Converter |
| ADS1256IDBR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1256IDBRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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