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參數(shù)資料
| 型號： | ADS1222IPWT |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 24BIT ADC W/2CH MUX 14-TSSOP |
| 產品培訓模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標準包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 240 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，雙極 |
| 其它名稱： | 296-17321-6 |
ADS1222
SBAS314B APRIL 2004 REVISED JANUARY 2009
www.ti.com
12
To help see the response at lower frequencies,
Figure 21 illustrates the response out to 1kHz. Notice
that signals at multiples of 120Hz are rejected. The
ADS1222 data rate and frequency response scale
directly with CLK frequency. For example, if fCLK
increases from 2MHz to 4MHz, the data rate increases
from 120SPS to 240SPS, while the notches increase
from 120Hz to 240Hz.
Input Frequency (Hz)
Ga
in
(d
B
)
0
20
40
60
80
100
500
600
700
800
900
100
200
300
400
1k
0
Figure 21. Frequency Response to 1kHz
Rejecting 50Hz or 60Hz noise is as simple as choosing
the clock frequency. If simultaneous rejection of 50Hz
and 60Hz noise is desired, fCLK = 910kHz can be
chosen. The data rate becomes 54.7SPS and the
frequency response of the ADS1222 rejects the 50Hz
and 60Hz noise to below 60dB. The frequency
response of the ADS1222 near 50Hz and 60Hz with
fCLK = 910kHz is shown in Figure 22.
Input Frequency (Hz)
Ga
in
(d
B
)
0
20
40
60
80
100
80
30
40
50
60
70
Figure 22. Frequency Response Near 50Hz and
60Hz with fCLK = 910kHz
SETTLING TIME
After changing the input multiplexer, selecting the input
buffer, or using temperature sensor, the first data is fully
settled. In the ADS1222, the digital filter is allowed to
settle after toggling any of the MUX, BUFEN, or
TEMPEN pins. Toggling of any of these digital pins will
cause the input to switch to the proper channel, start
conversions, and hold the DRDY/DOUT line high until
the digital filter is fully settled. For example, if MUX
changes from low to high, selecting a different input
channel, DRDY/DOUT immediately goes high and the
conversion process restarts. DRDY/DOUT goes low
when fully settled data is ready for retrieval. There is no
need to discard any data. Figure 23 shows the timing of
the DRDY/DOUT line as the input multiplexer changes.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t1(1)
Settling time (DRDY/DOUT held high) after a change in any of the
25.9
26.4
ms
MUX, BUFEN, or TEMPEN pins
(1) Values given for fCLK = 2MHz. For different fCLK frequencies, scale proportional to CLK period.
Abrupt change in internal V
IN due to status change (for example, switch channels, temp sensor, buffer enable)
ADS1222 holds DRDY/DOUT
until digital filter settles
MUX0
V
IN
t
1
DRDY/DOUT
DRDY/DOUT suppressed after status change
Fully settled
data ready
Figure 23. Example of Settling Time After Changing the Input Multiplexer
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1222IPWT | 制造商:Texas Instruments 功能描述:IC 24-BIT ADC 2 CH DIFF I/P MULTI |
| ADS1222IPWTG4 | 功能描述:模數(shù)轉換器 - ADC 24-Bit Conv w/2-Ch Diff Input Mltplxer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1224 | 制造商:BB 制造商全稱:BB 功能描述:24-Bit Analog-to-Digital Converter with 4-Channel Differential Input Multiplexer |
| ADS1224EVM | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 ADS1224 Eval Mod RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1224IPWR | 功能描述:模數(shù)轉換器 - ADC 24-bit 240SPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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