參數(shù)資料
型號(hào)： ADRF6604ACPZ-R7
廠商： ANALOG DEVICES INC
元件分類： 混頻器
英文描述： 2500 MHz - 2900 MHz RF/MICROWAVE DOUBLE BALANCED MIXER
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD2, LFCSP_VQ, CP-40
文件頁(yè)數(shù)： 22/24頁(yè)
文件大?。?/td> 714K
代理商： ADRF6604ACPZ-R7
ADRF6604
Rev. 0 | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A
LOW IMPEDANCE GROUND PLANE.
1
VCC1
2
DECL3P3
3
CP
4
GND
5
RSET
6
REF_IN
7
GND
8
MUXOUT
9
DECL2P5
10
VCC2
23 GND
24 GND
25 GND
26 RFIN
27 VCC_V2I
28 GND
29 IP3SET
30 GND
22 VCC_MIX
21 GND
11
G
ND
12
DAT
A
13
CL
K
15
G
ND
17
V
CC_L
O
16
PL
L
_
EN
18
IFP
19
IFN
20
G
ND
14
LE
33
NC
34
V
CC_L
O
35
G
ND
36
L
O
DRV
_E
N
37
LON
38
LOP
39
V
T
UNE
40
DE
CL
V
CO
32
NC
31
G
ND
TOP VIEW
(Not to Scale)
ADRF6604
08553-
003
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCC1
Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin.
2
DECL3P3
Decoupling Node for the 3.3 V LDO. Connect a 0.1 F capacitor between this pin and ground.
3
CP
Charge Pump Output Pin. Connect to VTUNE through the loop filter.
4, 7, 11, 15, 20,
21, 23, 24, 25,
28, 30, 31, 35
GND
Ground. Connect these pins to a low impedance ground plane.
5
R
SET
Charge Pump Current. The nominal charge pump current can be set to 250 A, 500 A, 750 A, or 1 mA
using Bits[DB11:DB10] in Register 4 and by setting Bit DB18 to 0 (internal reference current). In this mode,
no external R
SET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be
externally adjusted according to the following equation:
×
=
8
.
37
4
.
217
NOMINAL
CP
SET
I
R
6
REF_IN
Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz.
8
MUXOUT
Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect
signal. The output is selected by programming Bits[DB23:DB21] in Register 4.
9
DECL2P5
Decoupling Node for the 2.5 V LDO. Connect a 0.1 F capacitor between this pin and ground.
10
VCC2
Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin.
12
DATA
Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits.
13
CLK
Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. The maximum clock frequency is 20 MHz.
14
LE
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the
eight registers. The relevant latch is selected by the three control bits of the 24-bit word.
16
PLL_EN
PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is
automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the
internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be
used to switch modes.
17, 34
VCC_LO
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 F capacitor located close to the pin.
18, 19
IFP, IFN
Mixer IF Outputs. These outputs should be pulled to VCC_MIX with RF chokes.
22
VCC_MIX
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 F capacitor located close to the pin.
26
RF
IN
RF Input (Single-Ended, 50 Ω).
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