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參數(shù)資料
| 型號： | ADP3422 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-TSSOP -40 to 110 |
| 中文描述： | 國際汽車計劃- II標(biāo)準(zhǔn)的核心電源控制器，用于移動CPU |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 174K |
| 代理商： | ADP3422 |
REV. 0
ADP3422
–6–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
HYSSET
Hysteresis Set. This is an analog I/O pin whose output is a voltage reference and whose input is a
current that is programmed by an external resistance to ground. The current is used in the IC to set
the hysteretic currents for the Core Comparator and the Current Limit Comparator. Modification of the
resistance will affect both the hysteresis of the feedback regulation and the current limit set point and
hysteresis. The application circuit suggests a resistor divider, as this pin’s functionality is used to supply a
divided reference voltage to another high-impedance pin.
CPU Set. This is a high-impedance analog input pin to which a reference voltage is applied via a
resistor divider (e.g., from the HYSSET pin). The applied reference to this pin sets a threshold that
lies between two VID codes, each of which represents the Battery Optimized Mode (
BOM
) VID code
of a certain CPU. At startup of the CPU regulator, the
BOM
VID code is received and the corresponding
DACOUT voltage is compared against the CPUSET voltage. The type of CPU is then categorized
as being in one of two frequency categories, the lower of which has a lower
BOM
VID code. The
information is latched into the IC and, if the lower frequency CPU has been detected, is used to add
a downward shift of the regulated core voltage to the optimum level. The shift is performed using the
FSHIFT and RAMP pins.
Frequency Shift. This is an analog I/O pin whose output is a voltage reference and whose input is a
current that is programmed by an external resistance to ground. The current is used in the IC to
set a switched bias current out of the RAMP pin, depending on whether it is activated by the
latched function of the CPUSET pin. When activated, this added bias current creates a downward
shift of the regulated core voltage to a predetermined optimum level for regulation corresponding
to the frequency range of the CPU.
Deep Sleep Shift. This is an analog I/O pin whose output is a voltage reference and whose input is a
current that is programmed by an external resistance to ground. The current is used in the IC to
set a switched bias current out of the RAMP pin, depending on whether it is activated by the
DSLP
signal. When activated, this added bias current creates a downward shift of the regulated core voltage
to a predetermined optimum level for regulation corresponding to Deep Sleep mode of CPU operation.
Battery Optimized Mode Shift. This is an analog I/O pin whose output is a voltage reference and
whose input is a current that is programmed by an external resistance to ground. The current is
used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by
the
BOM
signal. When activated, this added bias current creates a downward shift of the regulated core
voltage to a predetermined optimum level for regulation corresponding to Battery Optimized Mode of
CPU operation.
VID Input. Most significant bit.
VID Input
VID Input
VID Input
VID Input. Least significant bit.
Battery Optimized Mode (active low). This is a digital input pin coming from a system signal
corresponding to Battery Optimized Mode of the CPU operation in its active low state and Performance
Optimized Mode (POM) in its disactivated high state. The signal controls the optimal positioning
of the core voltage regulation level according to the functionality of the BSHIFT and RAMP pins.
It is also used to initiate a blanking period for the PWRGD signal (to disable its response to a pending
dynamic core voltage change according to the VID code) whenever a signal transition occurs.
Deep Sleep Mode (active low). This is a digital input pin coming from a system signal which, in
its active state, corresponds to Deep Sleep mode of the CPU, which is a subset operating mode of
either
BOM
or POM operation. The signal controls the optimal positioning of the core voltage regulation
level according to the functionality of the DSHIFT and RAMP pins.
2
CPUSET
3
FSHIFT
4
DSHIFT
5
BSHIFT
6
7
8
9
10
11
VID4
VID3
VID2
VID1
VID0
BOM
12
DSLP
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