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參數(shù)資料
| 型號： | ADP3422 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-TSSOP -40 to 110 |
| 中文描述： | 國際汽車計劃- II標(biāo)準(zhǔn)的核心電源控制器，用于移動CPU |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 174K |
| 代理商： | ADP3422 |
REV. 0
ADP3422
–10–
APPLICATION INFORMATION
This application section presents both the theoretical background
and the detailed procedure for designing dc/dc converters with
the ADP3422 controller for mobile CPUs. The ADP3422 is
used in a unique ripple regulator (also called hysteretic regulator)
configuration, which allows employing ADOPT, Analog Devices’
optimal voltage positioning technique to implement the output
desired voltage impedance statically and dynamically, as required
by Intel’s IMVP-2 specification.
Hysteretic Regulator
Figure 1 shows the conventional hysteretic regulator and the
characteristic waveforms. The operation is as follows. During
the time the upper transistor, Q1, is turned on, the inductor
current, I
L
, and also the output voltage, V
OUT
, increase. When
V
OUT
reaches the upper threshold of the hysteretic comparator,
Q1 is turned off, Q2 is turned on, and the inductor current and also
the output voltage begin to decrease. The cycle repeats after
V
OUT
reaches the lower threshold of the hysteretic comparator.
C
O
R
E
V
H
V
REF
Q1
Q2
V
SW
LOAD
V
IN
L
I
L
V
OUT
V
OUT
V
H
V
SW
I
L
Figure 1. Conventional Hysteretic Regulator and Its
Characteristic Waveforms
The switching frequency is determined by the equivalent series
resistance R
E
of the output capacitor, the inductance L of the
inductor, the input and output voltages, and the hysteresis
V
H
of the comparator. It is as follows:
f
R
LV
V
(
V
V
V
)
E
H
IN
OUT
OUT
IN
=
–
(1)
Since there is no voltage-error amplifier in the hysteretic regulator,
its response to any change in the load current or the input volt-
age is virtually instantaneous. Therefore, the hysteretic regulator
represents the fastest possible dc/dc converter control technique.
A slight disadvantage of the hysteretic regulator is that its frequency
varies with the input and output voltages. In a typical mobile CPU
converter application, the worst-case frequency variation due to
the input voltage variation is in the order of 30%, which is usu-
ally acceptable. In the simplest implementation of the hysteretic
converter, shown in Figure 1, the frequency also varies propor-
tionally with the ESR of the output capacitor. Since the initial value
is often poorly controlled, and the ESR of electrolytic capacitors
also changes with temperature and age, practical ESR variations
can easily lead to a frequency variation on the order of three to
one. However, using the ADP3422 controller in a modified
hysteretic topology eliminates the dependence of the operating
frequency on the ESR. In addition, the modification allows the
optimal implementation, ADOPT, of the Intel
’
s IVMP-2 load-line
specification. Figure 2 shows the modified hysteretic regulator.
C
OC
R
D
V
H
V
REF
Q1
Q2
R
CS
LOAD
V
IN
L
I
L
V
OUT
R
C
C
O
R
E
Figure 2. Modified Hysteretic Regulator with ADOPT
The implementation requires adding a resistive divider (R
C
and
R
D
) between the reference voltage and the output, and connecting
the tap of the divider to the noninverting input of the hysteretic
comparator. A capacitor, C
OC
, is placed across the upper mem-
ber (R
C
) of the divider.
It is easily shown that the output impedance of the converter can
be no less than the ESR of the output capacitor. A straightfor-
ward derivation demonstrates that the output impedance of the
converter in Figure 2 can be minimized to equal the ESR, R
E
,
when the following two equations are valid (neglecting PCB
trace resistance for now):
R
R
R
R
R
D
C
E
CS
CS
=
–
(2)
and
C
C R
R R
OC
E
D
=
2
(3)
From (3), the series resistance is:
R
R
R
R
CS
E
D
C
=
+
1
(4)
This is the ADOPT configuration and design procedure that
allows the maximum possible ESR to be used while meeting a
given load-line specification.
It can be seen from (4) that unless R
D
is zero or R
C
is infinite,
R
CS
will be always smaller than R
E
. An advantage of the circuit
of Figure 2 is that if we select the ratio R
D
/R
C
well above unity,
the additional dissipation introduced by the series resistance R
CS
will be negligible. Another interesting feature of the circuit in
Figure 2 is that the ac voltage across the two inputs of the hys-
teretic comparator is now equal only to the ac voltage across
R
CS
. This is due to the presence of the capacitor C
OC
, which
effectively couples the ac component of the output voltage to the
noninverting input voltage of the comparator. Since the com-
parator sees only the ac voltage across R
CS
, in the circuit of
Figure 2 the dependence of the switching frequency on the ESR
of the output capacitor is completely eliminated. Equation (5)
presents the expression for the switching frequency.
f
R
LV
V
(
V
V
V
)
CS
H
IN
OUT
OUT
IN
=
–
(5)
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