- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374022 > ADP3367AR (ANALOG DEVICES INC) 2nd Level Over Voltage Protection for 2, 3, or 4 Cell LiIon & LiPoly Batteries (2nd Lev Protection) 8-SM8 PDF資料下載
參數(shù)資料
| 型號(hào)： | ADP3367AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 2nd Level Over Voltage Protection for 2, 3, or 4 Cell LiIon & LiPoly Batteries (2nd Lev Protection) 8-SM8 |
| 中文描述： | FIXED/ADJUSTABLE POSITIVE LDO REGULATOR, 0.5 V DROPOUT, PDSO8 |
| 封裝： | SOP-8 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 148K |
| 代理商： | ADP3367AR |
ADP3367
–6–
REV. 0
+
C1
10μF
IN
OUT
LBO
ADP3367
+5V
OUTPUT
R2
10k
LBI
GND
SET
SHDN
DROPOUT
STATUS
OUTPUT
DD
V
IN
R1
100k
+
Figure 11. Dropout Status Output
Output Capacitor
An output capacitor is required on the ADP3367 to maintain sta-
bility and also to improve the load transient response. Capacitor
values from 10
μ
F upwards are recommended. Capacitors larger
than 10
μ
F will further improve the transient response. T antalum
or aluminum electrolytics are suitable for most applications. For
temperatures below about –25
°
C, solid tantalums should be used
as many aluminum electrolytes freeze at this temperature.
Quiescent Current Considerations
T he ADP3367 uses a PNP output stage to achieve low dropout
voltages combined with high output current capability. Under
normal regulating conditions the quiescent current is extremely
low. However if the input voltage drops so that it is below the
desired output voltage, the quiescent current increases consider-
ably. T his happens because regulation can no longer be main-
tained and large base current flows in the PNP output transistor
in an attempt to hold it fully on. For minimum quiescent cur-
rent, it is therefore important that the input voltage is main-
tained higher than the desired output level. If the device is being
powered using a battery that can discharge down below the rec-
ommended level, there are a couple of techniques that can be
applied to reduce the quiescent current, but at the expense of
dropout voltage. T he first of these is illustrated in Figure 12. By
connecting DD to SHDN the regulator is partially disabled with
input voltages below the desired output voltage and therefore
the quiescent current is reduced considerably.
+
C1
10μF
IN
OUT
ADP3367
+5V
OUTPUT
GND
SET
SHDN
DD
V
IN
R1
47k
+
C2
0.1μF
Figure 12. IQ Reduction 1
Another technique for reducing the quiescent current near drop-
out is illustrated in Figure 13. T he DD output is used to modify
the output voltage so that as V
IN
drops, the desired output volt-
age setpoint also drops. T his technique only works when exter-
nal resistors are used to set the output voltage. With V
IN
greater
than V
OUT
, DD has no effect. As V
IN
reduces and dropout is
reached, the DD output starts sourcing current into the SET
input through R3. T his increases the SET voltage so that the
regulator feedback loop does not drive the internal PNP transis-
tor as hard as it otherwise would. As the input voltage continues
to decrease, more current is sourced, thereby reducing the PNP
drive even further. T he advantage of this scheme is that it main-
tains a low quiescent current down to very low values of V
IN
at
which point the batteries are well outside their useful operating
range. T he output voltage tracks the input voltage minus the
dropout. T he SHDN function is also unaffected and may be
used normally if desired.
+
C1
10μF
IN
OUT
ADP3367
+5V
OUTPUT
GND
SET
SHDN
DD
R1
610k
R2
2M
R3
1M
+
V
IN
QUIESCENT CURRENT BELOW DROPOUT
01
6
2
3
5
400
200
900
1mA
800
700
600
500μA
300
100
4
1.2mA
900μA
V
IN
– V
G
Figure 13. IQ Reduction 2
POWE R DISSIPAT ION
T he ADP3367 can supply currents up to 300 mA and can oper-
ate with input voltages as high as 16.5V, but not simultaneously.
It is important that the power dissipation and hence the internal
die temperature be maintained below the maximum limits. Power
Dissipation is the product of the voltage differential across the
regulator times the current being supplied to the load. T he
maximum package power dissipation is given in the Absolute
Maximum Ratings. In order to avoid excessive die temperatures,
these ratings must be strictly observed.
P
D
= (V
IN
– V
OUT
) (I
L
)
T he die temperature is dependent on both the ambient tempera-
ture and on the power being dissipated by the device. T he inter-
nal die temperature must not exceed 125
°
C. T herefore, care
must be taken to ensure that, under normal operating condi-
tions, the die temperature is kept below the thermal limit.
T
J
=
T
A
+
P
D
(
θ
J A
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADP3404ARU | GSM Power Management System |
| ADP3404 | GSM Power Management System |
| ADP3405ARU | Replaced by BQ29412 : Voltage Protection for 2-,3-or,4-Cell Lion Batteries (2nd Protection) 8-TSSOP -20 to 85 |
| ADP3405 | Replaced by BQ29412 : Voltage Protection for 2-,3-or,4-Cell Lion Batteries (2nd Protection) 8-TSSOP -20 to 85 |
| ADP3408ARU-25 | GSM Power Management System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADP3367AR-REEL | 制造商:Analog Devices 功能描述:LDO Regulator Pos 1.3V to 16V5V 0.2A 8-Pin SOIC N T/R |
| ADP3367AR-REEL7 | 制造商:Analog Devices 功能描述:LDO Regulator Pos 1.3V to 16V5V 0.2A 8-Pin SOIC N T/R |
| ADP3367ARZ | 功能描述:IC REG LDO 5V/ADJ .2A 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):正，固定式 輸出電壓:8V 輸入電壓:10.5 V ~ 23 V 電壓 - 壓降（標(biāo)準(zhǔn)）:1.7V @ 40mA 穩(wěn)壓器數(shù)量:1 電流 - 輸出:100mA（最小值） 電流 - 限制（最?。?- 工作溫度:0°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1075 (CN2011-ZH PDF) 其它名稱:296-24390-1 |
| ADP3367ARZ | 制造商:Analog Devices 功能描述:LDO 2.5-16.5V 0.3VDO 0.3A 8SOIC |
| ADP3367ARZ-REEL | 制造商:Analog Devices 功能描述:LDO Regulator Pos 1.3V to 16V5V 0.2A 8-Pin SOIC N T/R |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。