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參數(shù)資料
| 型號(hào)： | ADNS-5030 |
| 廠商： | Avago Technologies Ltd. |
| 英文描述： | Low Power Optical Mouse Sensor |
| 中文描述： | 低功率光學(xué)鼠標(biāo)傳感器 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 366K |
| 代理商： | ADNS-5030 |
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, V
DD
= 3.3 V.
Parameter
Symbol MinimumTypical MaximumUnits Notes
Reset Pulse Width
t
RESET
250
Motion Delay after Reset
t
MOT-RST
Forced Rest Enable
t
REST-EN
Wake from Forced Rest
t
REST-DIS
Power Down
t
PD
Wake from Power Down
t
WAKEUP
50
MISO Rise Time
t
r-MISO
40
MISO Fall Time
t
f-MISO
40
MISO Delay after SCLK
t
DLY-MISO
MISO Hold Time
t
hold-MISO
0.5
MOSI Hold Time
t
hold-MOSI
200
MOSI Setup Time
t
setup-MOSI
120
SPI Time between Write
t
SWW
30
Commands
SPI Time between Write and
t
SWR
20
Read Commands
SPI Time between Read
t
SRW
250
and Subsequent Commands
t
SRR
SPI Read Address-Data
t
SRAD
4
Delay
NCS Inactive after Motion
t
BEXIT
250
Burst
NCS to SCLK Active
t
NCS-SCLK
120
SCLK to NCS Inactive
t
SCLK-NCS
120
(for Read Operation)
SCLK to NCS Inactive
t
SCLK-NCS
20
(for Write Operation)
NCS to MISO high-Z
t
NCS-MISO
Transient Supply Current
I
DDT
50
1
1
50
55
200
200
120
1/f
SCLK
250
60
ns
ms
s
s
ms
ms
ns
ns
ns
μs
ns
ns
μs
μs
ns
μs
ns
ns
ns
μs
ns
mA
Active low
From NRESET pull high to valid motion, assuming
V
DD
and motion is present
From Rest Mode(RM) bits set to target rest mode
From Rest Mode(RM) bits cleared to valid motion
From PD (when bit 1 of register 0x0d is set) to
low current
From PD inactive (when NRESET pin is asserted low to
high or write 0x5a to register 0x3a) to valid motion
C
L
= 100 pF
C
L
= 100 pF
From SCLK falling edge to MISO data valid, no load
conditions
Data held until next falling SCLK edge
Amount of time data is valid after SCLK rising edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second data byte
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second address byte
From rising SCLK for last bit of the first data byte, to
falling SCLK for the first bit of the next address
From rising SCLK for last bit of the address byte,
to falling SCLK for first bit of data being read
Minimum NCS inactive time after motion burst before
next SPI usage
From NCS falling edge to first SCLK rising edge
From last SCLK rising edge to NCS rising edge,
for valid MISO data transfer
From last SCLK rising edge to NCS rising edge,
for valid MOSI data transfer
From NCS rising edge to MISO high-Z state
Max supply current during a V
DD
ramp from 0 to V
DD
Figure 9. Distance from lens reference plane to tracking surface (Z).
2.40
(0.094)
Z =
OBJECT SURFACE
SENSOR
LENS
LENS REFERENCE PLANE
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