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參數資料
| 型號： | ADNS-2051 |
| 英文描述： | Optical Mouse Sensor |
| 中文描述： | 光學鼠標傳感器 |
| 文件頁數： | 22/40頁 |
| 文件大?。?/td> | 454K |
| 代理商： | ADNS-2051 |
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and is expecting a value of 0x02.
If it receives this value, it then
knows that the communication to
the ADNS-2051 is operational.
The problem occurs if the
ADNS-2051 powers up before the
microprocessor sets the SCLK
and SDIO lines to be outputs and
high. The ADNS-2051 sees the
raising of the SCLK as a valid
rising edge, and clocks in the
state of the SDIO as the first bit
of the address (sets either a read
or a write depending upon the
state).
In the case of SDIO low, then a
read operation has started. When
the microprocessor begins to
actually send the address, the
ADNS-2051 already has the first
bit of an address. When the sev-
enth bit is sent by the micro, the
ADNS-2051 has a valid address,
and drives the SDIO line high
within 120 ns (see detail “A” in
Figure 27 and Figure 28). This
results in a bus fight for SDIO.
Since the address is wrong, the
data sent back will be incorrect.
In the case of SDIO high, a write
operation is started. The address
and data are out of synchroniza-
tion, and the wrong data will be
written to the wrong address.
Two Solutions
There are two different ways to
solve the problem, waiting for the
serial port watchdog timer to
time out, or using the PD line to
reset the serial port.
1. Serial Port Watchdog Timer
Timeout
Figure 36. Power up serial port watchdog timer sequence.
Figure 37. Power up serial port PD sync sequence.
DATA = 0x02
SCLK
SDIO
ADDRESS = 0x00
PD
V
DD
> t
SPTT
If the microprocessor waits at
least t
SPTT
from V
DD
valid, it will
ensure that the ADNS-2051 has
powered up and the watchdog
timer has timed out. This
assumes that the microprocessor
and the ADNS-2051 share the
same power supply. If not, then
the microprocessor must wait
t
SPTT
from ADNS-2051 V
DD
valid. Then when the SCLK
toggles for the address, the
ADNS-2051 will be in sync with
the microprocessor.
2. PD Sync
DATA = 0x02
SCLK
SDIO
ADDRESS = 0x00
PD
V
DD
4 ms
The PD line can be used to resync
the serial port. If the micropro-
cessor waits for 4 ms from V
DD
valid, and then outputs a valid PD
pulse (see Figure 15), then the
serial port will be ready for data.
Resync Note
If the microprocessor and the
ADNS-2051 get out of sync, then
the data either written or read
from the registers will be incor-
rect. An easy way to solve this is
to output a PD pulse to resync
the parts after an incorrect read.
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