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參數(shù)資料
| 型號(hào)： | ADN2891ACPZ-500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP LIM 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 限制 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | 2.9 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ EP（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADN2891ACPZ-500RL7DKR |
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ADN2891
Rev. A | Page 11 of 16
APPLICATIONS
PCB DESIGN GUIDELINES
The exposed pad should connect to the GND plane using filled
vias so that solder does not leak through the vias during reflow.
Using filled vias in parallel under the package greatly reduces
the thermal resistance and enhances the reliability of the
connectivity of the exposed pad to the GND plane during
reflow.
Proper RF PCB design techniques must be used to ensure
optimal performance.
Output Buffer Power Supply and Ground Planes
Pin 9 (DRVEE) and Pin 12 (DRVCC) are the power supply and
ground pins that provide current to the differential output
buffer. To reduce possible series inductance, Pin 9, which is the
ground return of the output buffer, should connect to ground
directly. If the ground plane is an internal plane and
connections to the ground plane are vias, multiple vias in
parallel to ground can reduce series inductance.
To reduce power noise, a 10 μF electrolytic decoupling capacitor
between power and ground should be close to where the 3.3 V
supply enters the PCB. The other 0.1 μF and 1 nF ceramic chip
decoupling capacitors should be close to the VCC and VEE pins
to provide better decouple filtering and a shorter current return
loop.
Similarly, to reduce the possible series inductance, Pin 12,
which supplies power to the high speed differential
OUTP/OUTN output buffer, should connect to the power plane
directly. If the power plane is an internal plane and connections
to the power plane are vias, multiple vias in parallel can reduce
the series inductance, especially on Pin 12. See Figure 20 for the
recommended connections.
05244-
008
CONNECT
EXPOSED
PAD TO
GND
AVCC
1
THRADJ
5
CAZ1
6
CAZ2
7
LOS
8
PD_
C
ATHODE
16
PD_VCC
15
RSSI_OUT
14
SQUELCH
13
PIN
2
NIN
3
AVEE
4
DRVCC
12
OUTN
10
DRVEE
9
OUTP
C4
C3
11
C2
C1
TO HOST
BOARD
C7
C8
VCC
C5
C6
VCC
C11
C12
R2
VCC
R3
4.7k
Ω TO 10kΩ
ON HOST BOARD
VCC
ADN2880
0.1
μF
VCC
C9
RSSI MEASUREMENT
TO ADC
R1
C10
C1–C4, C11: 0.01
μF X5R/X7R DIELECTRIC, 0201 CASE
C5, C7, C9, C10, C12: 0.1
μF X5R/X7R DIELECTRIC, 0402 CASE
C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE
ADN2891
Figure 20. Typical Applications Circuit (Example of Using PIN PD and On-Chip RSSI Detector)
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