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參數(shù)資料
| 型號： | ADN2860ACPZ25-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 3CH 25K 24-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 128，512，512 |
| 電阻（歐姆）： | 25k |
| 電路數(shù)： | 3 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | ADN2860ACPZ25RLCT |
ADN2860
Rev. B | Page 13 of 20
Table 6. RDAC R/W EEPROM Addresses (CMD/ REG = 0, EE/RDAC = 1)
A4
A3
A2
A1
A0
Byte Description
0
RDAC0 8 LSBs
0
1
RDAC0 MSB
0
1
0
RDAC1 8 LSBs
0
1
RDAC1 MSB
0
1
0
RDAC2 7 bits
0
1
0
1
11 bytes RDAC user EEPROM
…to…
0
1
Table 7. RDAC Command Table (CMD/REG = 1)
C3
C2
C1
C0
Command Description
0
NOP.
0
1
Restore EEPROM to RDAC.1
0
1
0
Store RDAC to EEPROM.2
0
1
Decrement RDAC 6 dB.
0
1
0
Decrement all RDACs 6 dB.
0
1
0
1
Decrement RDAC one step.
0
1
0
Decrement all RDACs one step.
0
1
Reset. Restore EEPROM to all RDACs.2
1
0
Increment RDAC 6 dB.
1
0
1
Increment all RDACs 6 dB.
1
0
1
0
Increment RDAC one step.
1
0
1
Increment all RDACs one step.
1
0
Reserved.
…to…
1
1 Command leaves the device in the EEPROM read power state. Issue the NOP command to return the device to the idle state.
2 Command requires acknowledge polling after execution.
RDAC Interface Operation
Each programmable resistor wiper setting is controlled by
specific RDAC registers, as shown in Table 5. Each RDAC
register corresponds to an EEPROM memory location, which
provides nonvolatile wiper storage functionality.
RDAC registers and their corresponding EEPROM memory
locations are programmed and read independently from each
other. The RDAC register is refreshed by the EEPROM locations,
either with a hardware reset via Pin 1, or by issuing one of the
various RDAC register load commands shown in the Table 7.
RDAC Write
Setting the wiper position requires an RDAC write operation,
shown in Figure 22. RDAC write operations follow a format
similar to the EEPROM write interface. The only difference
between an RDAC write and an EEPROM write operation is the
use of an RDAC address byte in place of the memory address
used in the EEPROM write operation. The RDAC address byte
As with the EEPROM write operation, any RDAC EEPROM
(Shortcut Command 2) write operation disables the I2C
interface during the internal write cycle. Acknowledge polling,
as described in the EEPROM Interface section, is required to
determine whether the write cycle is complete.
RDAC Read
The ADN2860 provides two RDAC read operations. The first,
shown in Figure 23, reads the contents of the current RDAC
address counter. Figure 24 illustrates the second read operation,
which allows users to specify which RDAC register to read by
first issuing a dummy write command to change the RDAC
address pointer, and then proceeding with the RDAC read
operation at the new address location.
The read-only RDAC EEPROM memory locations can also be
read by using the address and bits specified in Table 6.
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