參數(shù)資料
型號(hào)： ADN2860ACPZ25-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/20頁(yè)
文件大小： 0K
描述： IC POT DGTL 3CH 25K 24-LFCSP
標(biāo)準(zhǔn)包裝： 1
接片： 128，512，512
電阻（歐姆）： 25k
電路數(shù)： 3
溫度系數(shù)： 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-VQ（4x4）
包裝： 剪切帶 (CT)
其它名稱： ADN2860ACPZ25RLCT
ADN2860
Rev. B | Page 18 of 20
For RDAC0 and RDAC1:
()
W
AB
WB
R
D
R
+
×
=
512
(1)
For example, the following RDAC latch codes set the
corresponding output resistance values, which apply to
RAB = 25 kΩ digital potentiometers.
Table 12. RWA(d) at Selected Codes for RAB = 25 kΩ
D (DEC)
RWA(d) (Ω)
Output State
For RDAC2:
()
W
AB
WB
R
D
R
+
×
=
128
(2)
511
148.8
Full scale
256
12600
Midscale
1
25051
1 LSB
0
25100
Zero scale
where:
D is the decimal equivalent of the data contained in the RDAC
register.
RW is the wiper resistance.
The typical distribution of RAB from channel to channel is ±0.1%
within the same package. Device-to-device matching is lot
dependent, with a worst-case variation of ±15%. RAB temp-
erature coefficient is 35 ppm/°C.
The output resistance values in Table 11 are set for the given
RDAC latch codes with VDD = 5 V, which applies to RAB = 25 kΩ
digital potentiometers.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
Table 11. RWB at Selected Codes for RWB_FS = 25 kΩ
D (DEC)
RWB(d) (Ω)
The digital potentiometer can be configured to generate an
output voltage at the wiper terminal, which is proportional to
the input voltages applied to the A and B terminals. Connecting
the A terminal to 5 V and the B terminal to ground produces an
output voltage at the wiper that can vary between 0 V to 5 V.
Each LSB of voltage is equal to the voltage applied across the A
and B terminals divided by the 2N position resolution of the
potentiometer divider.
Output State
511
25051
Full scale
256
12600
Midscale
1
148.8
1 LSB
0
100
Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. To avoid degradation or possible destruction
of the internal switches, care should be taken to limit the current
flow between Terminals W and B to no more than 20 mA
intermittently or 2 mA continuously.
Since the ADN2860 can operate from dual supplies, the general
equations defining the output voltage at VW with respect to
ground for any given input voltages applied to the A and B
terminals are as follows:
Channel-to-channel RWB matching is better than 0.1%. The
change in RWB with temperature has a 35 ppm/°C temperature
coefficient.
For RDAC0 and RDAC1:
()
B
AB
W
V
D
V
+
×
=
512
(5)
Like the mechanical potentiometer that the RDAC replaces, the
ADN2860 parts are totally symmetrical. The resistance between
the W wiper and the A terminal also produces a digitally con-
trolled complementary resistance, RWA. When RWA is used, the
B terminal can be floating or tied to the wiper. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch is increased in
value. The general transfer equations for this operation are as
follows:
For RDAC2:
()
B
AB
W
V
D
V
+
×
=
128
(6)
For RDAC0 and RDAC1:
()
W
AB
WB
R
D
R
+
×
=
512
(3)
Equation 5 assumes that VW is buffered to null the effect of
wiper resistance. Operation of the digital potentiometer in the
divider mode results in more accurate operation over
temperature. In this mode, the output voltage is dependent on
the ratio of the internal resistors, not on the absolute value;
therefore, the drift improves to 15 ppm/°C. There is no voltage
polarity restriction between the A, B, and W terminals as long
as the terminal voltage (VTERM) stays within VSS < VTERM < VDD.
For RDAC2:
()
W
AB
WB
R
D
R
+
×
=
128
(4)
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