
REV. B
ADMC401
–28–
lower harmonic distortion in three-phase PWM inverters. This
technique also permits closed loop controllers to change the
average voltage applied to the machine windings at a faster rate
and so permits faster closed loop bandwidths to be achieved.
The operating mode of the PWM block (single or double update
mode) is selected by a control bit in MODECTRL register.
The PWM generator of the ADMC401 also provides an output
pulse on the PWMSYNC pin, which is synchronized to the PWM
switching frequency. In single update mode a PWMSYNC pulse
is produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse is
programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMC401 can be shut off
in a number of different ways. First, there is a dedicated asyn-
chronous PWM shutdown pin,
PWMTRIP
, that, when brought
LO, instantaneously places all six PWM outputs in the OFF
state (as determined by the state of the PWMPOL pin). In
addition, each of the PIO lines of the ADMC401 (PIO0 to
PIO11) can be configured to act as an additional PWM shut-
down. By setting the appropriate bit in the PIOPWM register,
the corresponding PIO line acts as an asynchronous PWM shut-
down source in a manner identical to the
PWMTRIP
pin. These
two hardware shutdown mechanisms are asynchronous so that
the associated PWM disable circuitry does not go through any
clocked logic, thereby ensuring correct PWM shutdown even in
the event of a loss of the DSP clock. In addition to the hardware
shutdown features, the PWM system may be shut down in soft-
ware by writing to the PWMSWT register.
Status information about the PWM system of the ADMC401 is
available to the user in the SYSSTAT register. In particular, the
state of the
PWMTRIP
and PWMPOL pins is available, as well
as status bits that indicates whether operation is in the first half
or the second half of the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 21. The generation of the six output PWM signals on
pins AH to CL is controlled by four important blocks:
The Three-Phase PWM Timing Unit, which is the core of
the PWM controller, generates three pairs of complemented
and dead time adjusted center based PWM signals.
The Output Control Unit allows the redirection of the out-
puts of the Three-Phase Timing Unit for each channel to
either the high side or the low side output. In addition, the
Output Control Unit allows individual enabling/disabling of
each of the six PWM output signals.
The Gate Drive Unit provides the correct polarity output
PWM signals based on the state of the PWMPOL pin. The
Gate Drive Unit also permits the generation of the high-
frequency chopping frequency and its subsequent mixing
with the PWM signals.
The PWM Shutdown Controller takes care of the various
PWM shutdown modes (via the
PWMTRIP
pin, the PIO
lines or the PWMSWT register) and generates the correct
RESET
signal for the Timing Unit.
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, t
CK
and is capable of generating two
interrupts to the DSP core. One interrupt is generated on the
occurrence of a rising edge of the PWMSYNC pulse and the
other is generated on the occurrence of any PWM shutdown
action.
AH
AL
PWMCHA (15
…
0)
PWMCHB (15
…
0)
PWMCHC (15
…
0)
PWMSEG
(8
…
0)
PWMGATE
(9
…
0)
THREE-PHASE
PWM TIMING
UNIT
OUTPUT
CONTROL
UNIT
CLK SYNC
RESET
SYNC
GATE
DRIVE
UNIT
CLK
POL
CLKOUT
PWMTM (15
…
0)
PWMDT (9
…
0)
PWMPD(9
…
0)
PWMSYNCWT(7
…
0)
MODECTRL (6)
PWMSWT
(0)
PIOPWM
(11
…
0)
BH
BL
CH
CL
PWMTRIP
PIO0
PWMSYNC
PWMPOL
PIO11
TO INTERRUPT
CONTROLLER
PWM
CONFIGURATION
REGISTERS
PWM
DUTY CYCLE
REGISTERS
PWMSYNC
PWMTRIP
PWM SHUTDOWN CONTROLLER
SR
PWMSR
OR
PIO
PWM
DETECT
Figure 21. Overview of the ADMC401 PWM Controller
THREE-PHASE TIMING UNIT
The 16-bit three-phase timing unit is the core of the PWM
controller and produces three pairs of pulsewidth modulated
signals with high resolution and minimal processor overhead.
The outputs of this timing unit are active LO such that a low
level is interpreted as a command to turn ON the associated
power device. There are four main configuration registers
(PWMTM, PWMDT, PWMPD and PWMSYNCWT) that
determine the fundamental characteristics of the PWM outputs.
In addition, the operating mode of the PWM (single or double
update mode) is selected by Bit 6 of the MODECTRL register.
These registers, in conjunction with the three 16-bit duty cycle
registers (PWMCHA, PWMCHB and PWMCHC), control the
output of the three-phase timing unit.
PWM Switching Frequency, PWMTM Register
The PWM switching frequency is controlled by the 16-bit PWM
period register, PWMTM. The fundamental timing unit of the
PWM controller is t
CK
(DSP instruction rate). Therefore, for a
26 MHz CLKOUT, the fundamental time increment is 38.5 ns.
The value written to the PWMTM register is effectively the
number of t
CK
clock increments in half a PWM period. The
required PWMTM value as a function of the desired PWM
switching frequency (f
PWM
) is given by:
PWMTM
f
f
f
f
CLKOUT
×
2
PWM
CLKIN
PWM
=
=
Therefore, the PWM switching period, T
s
, can be written as:
T
PWMTM t
S
CK
= ×
2